Tuesday, July 23, 2024

Strategies to Establish and Right Uneven Wafer Map Defects Brought on by Design and Course of Errors

Strategies to Establish and Right Uneven Wafer Map Defects Brought on by Design and Course of Errors


JAMES KIM, Senior Semiconductor and Course of Integration Engineer | Lam Analysis

Asymmetries in wafer map defects are normally handled as random manufacturing {hardware} defects. For instance, uneven wafer defects might be brought on by particles inadvertently deposited on a wafer throughout any variety of course of steps. On this article, I need to share a unique mechanism that may trigger wafer defects. Particularly, that these defects might be structural defects which are brought on by a biased deposition or etch course of.

It may be tough for a course of engineer to find out the reason for downstream structural defects situated at a particular wafer radius, notably if these defects are situated in various instructions or at totally different areas on the wafer. As a wafer construction is shaped, course of habits at that location might fluctuate from different wafer areas primarily based upon the radial path and particular wafer location. Slight variations in processes at totally different wafer areas might be exaggerated by the buildup of different course of steps as you progress towards that location. As well as, course of efficiency variations (reminiscent of variation in gear efficiency) may trigger on-wafer structural variability.

On this examine, structural defects can be nearly launched on a wafer to offer an instance of how structural defects might be created by variations in wafer location. We’ll then use our digital course of mannequin to determine an instance of a mechanism that may trigger a majority of these uneven wafer map defects.

Strategies

Determine 1. Anisotropic liner/barrier metallic
deposition on a tilted construction brought on by wafer warping

A 3D course of mannequin of a particular metallic stack (Cu/TaN/Ta) on a warped wafer was created utilizing SEMulator3D digital fabrication (Determine 1). After the 3D mannequin was generated, electrical evaluation of 49 websites on the wafer was accomplished.

In our mannequin, an anisotropic barrier/liner (TaN/Ta) deposition course of was used. As a consequence of wafer tilting, there have been TaN/Ta deposition variations seen throughout the simulated excessive side ratio metallic stack. To attenuate the variety of variables within the mannequin, Cu deposition was assumed to fill in a perfect method (with out voids). Forty-nine (49) corresponding 3D fashions have been created at totally different areas on the wafer, to replicate variations in tilting resulting from wafer warping. Subsequent, electrical simulation was accomplished on these 3D fashions to watch metallic line resistance at every location. Serpentine metallic line patterns have been constructed into the mannequin, to assist simulate the projected electrical efficiency on the warped wafer at totally different factors on the identical radius, and throughout totally different instructions on the wafer (Determine 2).

Figure 2 - Techniques to Identify and Correct Asymmetric Wafer Map Defects Caused by Design and Process Errors
Determine 2 – Strategies to Establish and Right Uneven Wafer Map Defects Brought on by Design and Course of Errors

Utilizing solely incoming construction and course of habits, we will develop a behavioral course of mannequin and prolong our gadget efficiency predictions and behavioral pattern evaluation exterior of our proposed course of window vary. Within the case of sophisticated processes with a couple of mechanism or habits, we will break up processes into a number of steps and develop fashions for every particular person course of step. There can be phenomena or habits in manufacturing that may’t be absolutely captured by the sort of course of modeling, however these fashions present helpful perception throughout course of window growth.

Outcomes

Of the 49 3D fashions, the fashions on the far fringe of the wafer have been closely tilted by wafer warpage. Curiously, not all the fashions on the similar wafer radius exhibited the identical habits. This was as a result of metallic sample design. With anisotropic deposition into excessive side ratio trenches, deposition in particular instructions was blocked at sure areas within the trenches (relying upon trench depth and tilt angle). This affected each the gadget construction and electrical habits at totally different areas on the wafer.

For the reason that metallic traces have been extending throughout the x-axis, there have been minimal variations seen when tilting the wafer throughout the x-axis in our mannequin. X-axis tilting created solely a small distinction in thickness of the Ta/TaN relative to the Cu. Nonetheless, when the wafer was tilted within the y-axis utilizing our mannequin, the excessive side ratio wall blocked Ta/TaN deposition as a result of deposition angle. This lowered the quantity of Ta/TaN deposition relative to Cu, which decreased the metallic resistance and positioned the resistance exterior of our design specification.

X-axis wafer tilting had little affect on the gadget construction. The resistance on the far fringe of the x-axis didn’t considerably change and remained in-spec. Y-axis wafer tilting had a extra important affect on the gadget construction. The resistance on the far fringe of the y-axis was exterior of our electrical specification (Determine 3).

Figure 3 - Techniques to Identify and Correct Asymmetric Wafer Map Defects Caused by Design and Process Errors
Determine 3 – Strategies to Establish and Right Uneven Wafer Map Defects Brought on by Design and Course of Errors

Conclusion

Though wafer warpage happens in a round method resulting from collected stress, sudden structural failures can happen in several radial instructions on the wafer resulting from variations in sample design and course of habits throughout the wafer. From this examine, we demonstrated that uneven buildings brought on by wafer warping can create top-bottom or left-right wafer efficiency variations, although processes have been uniformly utilized in a round distribution throughout the wafer.

Course of simulation can be utilized to raised perceive structural failures that may trigger efficiency variability at totally different wafer areas. A greater understanding of those structural failure mechanisms might help engineers enhance general wafer yield by taking corrective motion (reminiscent of performing line scanning at particular wafer areas) or by adjusting particular course of home windows to attenuate uneven wafer defects.

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