Friday, July 19, 2024

Single provide 200kHz VFC with bipolar differential inputs

Single provide 200kHz VFC with bipolar differential inputs



Few strategies for analog to digital conversion are extra “mature” than the traditional mixture of a voltage-to-frequency converter (VFC) with a counter. VFC digitization is of course integrating, so good noise rejection is inherent, as is programmable decision (if you need extra bits, simply depend longer). Sadly, and for a similar motive, excessive conversion pace isn’t. Correct, excessive decision, microsecond VFC conversion occasions are defiantly tough, however no less than millisecond charges are undoubtedly doable as proven on this design concept. 

Practically 4 many years in the past (in his Designs for Excessive Efficiency Voltage-to-Frequency Converters), famed analog guru Jim Williams cataloged 5 elementary strategies for voltage to frequency conversion. First on his listing, described as “most blatant”, was the “Ramp-Comparator” sort. Since I’ve all the time been a giant fan of the plain, the easy VFC proven in Determine 1 is a variation on that fundamental theme. It’s tailored for operation from a single provide rail, with handy and versatile differential bipolar inputs, and acceptable linearity whereas operating at frequencies as much as 200 kHz. Right here’s the way it works.

Determine 1 A Ramp-Comparator model 200 kHz VFC that operates from a single provide rail, with differential bipolar inputs, and a suitable linearity.

Wow the engineering world along with your distinctive design: Design Concepts Submission Information

A2, R1, and Q2 mix to make a precision (Q2 α~0.998) present sink with Q2 collector present:

Ic2 = (V1 –V2)/R1 = 100µA(V1 –V2)

Non-inverting enter V1 can vary from 0 to (2 – V2), has a properly excessive enter impedance (>1 TΩ) and a low bias present (10 pA). Inverting enter V2 has a decrease impedance (10 kΩ) however will settle for a voltage span from as optimistic as V1 to as unfavourable as (V1 – 2). If just one enter is used, the opposite ought to merely be grounded. Zero offset is about 200 µV (0.01%).

As proven in Determine 2 (yellow hint), Ic2 ramps 1-nF timing capacitor C1 from its reset voltage of three.5 V right down to the two.5-V set off stage offered by voltage reference U1. The ramp time required to do that is given by:

T = C1(3.5 – 2.5)/Ic2 = C1R1/(V1 – V2)
= 1nF 10k/(V1 – V2) = 10µs/(V1 – V2)
Fout = 1/T = 100kHz (V1 – V2) < 200kHz

Determine 2 VFC oscillation waveshapes the place: Vc1 is the VFC timing ramp, Fout is the output to counter, and A1p5 is the comparator’s non-inverting enter.

Comparator A1’s inverting enter is linked to C1, whereas its non-inverting enter watches the two.5-V reference. When the Vc1 ramp descends to 2.5 V, a sequence of (fairly fast) occasions are set in movement.

First, A1’s output transitions towards 5 V, finishing the transfer at 30 V/µsec in about 160 ns, the pace being enhanced by optimistic suggestions through C4. This supplies an output pulse (Determine 2 inexperienced hint) on Fout and activates Q3 to start the ramp-reset recharge of C1. In the meantime C3 {couples} Q3’s output to D1, reverse biasing the diode and briefly diverting Ic2 away from C1, which creates the humorous little flat spots seen on Determine 2’s yellow and purple traces. Extra on this later.

C1’s recharge present is routed through Q3’s emitter to Q1’s base, driving Q1 into saturation, precisely pulling R3’s high finish to +5 V and thereby A1’s non-inverting enter (pin 5) to 2.5(R5/(R3 + R5)) + 2.5 = 3.5 V (Determine 2 purple hint). C1 recharge continues till A1 pin 5 reaches pin 6’s 3.5 V, whereupon A1 switches again to 0, turning off Q3 (quick as a result of Q3 by no means saturates) and finishing the Fout pulse.

In the meantime, Q3’s turnoff has eliminated base drive from Q1, permitting it to get better from saturation (which takes about 500 ns consisting principally of storage time), flip off, and launch R3. This permits A1’s pin 5 to return to U1’s 2.5-V reference, the place it waits for the top of the following timeout and VFC cycle.

It additionally dumps built-in Ic2 cost amassed on C3 throughout ramp reset by means of D1 onto C1. The D1 C3 circuit characteristic thus cancels out an integral nonlinearity error that usually bedevils Ramp-Comparator VFCs as a result of cost misplaced through the ramp reset interval. Williams advises about this defect in his evaluation of the Ramp-Comparator topology “A critical disadvantage to this strategy is the capacitor’s discharge-reset time. This time, ‘misplaced’ within the integration, ends in vital linearity error… The D1 C3 connection prevents this nonlinearity by permitting integration of Ic2 to proceed uninterrupted throughout ramp reset, so no time is “misplaced”. Thanks for the warning, Jim!

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a great distance. Over 100 submissions have been accepted since his first contribution again in 1974.

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