Renesas has introduced the primary general-purpose 32-bit microcontroller household to be constructed round its in-house RISC-V processor core, the R9A02G021 vary — constructing atop its earlier application-specific designs and concentrating on power-sensitive and cost-conscious designs.
“From our RISC-V objective constructed ASSPs [Application-Specific Standard Products] to this new general-purpose MCU [Microcontroller Unit], our objective is to ship commercially viable merchandise that prospects can take to mass manufacturing shortly, whereas demonstrating the advantages for the RISC-V structure,” claims Renesas’ Daryl Khoo.
“As well as, prospects typically face with advanced design challenges and trade-offs resembling efficiency, energy consumption, reminiscence, or a selection of CPU structure. The brand new RISC-V MCU supplies a further diploma of option to prospects who wish to use merchandise with the open structure.”
Renesas’ in-house 32-bit RISC-V core is now out there in silicon, within the type of the R9A02G021 microcontroller. (📷: Renesas)
Renesas introduced its work on an in-house processor core design constructed across the free and open-source RISC-V instruction set structure (ISA) again in November 2023, promising silicon early this yr — now revealed because the R9A02G021 household. It wasn’t the corporate’s first RISC-V half, although: in March 2023 Renesas launched the R9A06G150, an ASSP designed for edge voice workloads utilizing a bought-in AndesCore D25F RISC-V core.
The R9A02G021, the primary utilizing Rensas’ personal core design, contains a single 32-bit processor core operating at as much as 48MHz and delivering a claimed 3.27 CoreMark per megahertz, has 16kB of static RAM of which 4kB has Error Correcting Code (ECC) assist, 128kB of code flash reminiscence, and 4kB of information flash. It features a 12-bit analog-to-digital converter (ADC) and eight-bit digital to analog converter (DAC), UART, SPI, I2C, and a software-configurable array unit (SAU).
Focusing on low-power tasks, the microcontrollers draw simply 162µA/MHz in energetic mode and 0.3µA in software program standby with a 4µS wakeup time. Assist is included in Renesas personal e² Studio built-in improvement setting (IDE), together with the IAR Embedded Workbench IDE and I-jet debug probe and Segger’s Embedded Studio IDE and J-Hyperlink debug probe. To reveal its capabilities, Renesas has additionally proven off a “Successful Mixture” reference design for an all-in-one good stress cooker.
Renesas has additionally launched a improvement board constructed across the new chip as a quick-start choice for prototyping. (📷: Renesas)
“Having developed our personal CPU core allows Renesas to optimize the implementation, offers full management of the design decisions, and secures the IP roadmap for future merchandise,” claims Renesas’ Giancarlo Parodi of the advantages from its shift to an in-house core design.
“Renesas has traditionally deep expertise in implementing CPUs for microcontrollers. This supplies buyer assurance on the deployment of commercially viable merchandise, supported by famend Renesas high quality, and eliminates any considerations about proprietary architectures.”
Extra info on the R9A02G021 elements is on the market on the Renesas web site; pricing begins at $2.70 earlier than quantity reductions. The corporate has additionally introduced the FPB-R9A02G021 RISC-V MCU Quick Prototyping Board for speedy improvement, priced at $17.29.
