Reference Design For Scalable 20.8 GSPS 12 Bit Digitizers

This reference design serves a number of purposes, together with oscilloscopes (DSOs), knowledge acquisition (DAQ) methods, and digital warfare, the place high-speed sign acquisition is vital. 

This reference design TIDA-010128 by Texas Devices (TI) outlines a high-performance 20.8 GSPS (Giga samples per second) sampling system utilizing RF-sampling analog-to-digital converters (ADCs) organized in a time-interleaved configuration. Time interleaving is a confirmed technique to realize larger sampling charges through the use of a number of ADCs to pattern at equally spaced intervals, combining their outputs for a better total sampling fee. Nonetheless, the interleaving technique introduces challenges in matching every ADC’s offset, achieve, and sampling time mismatch, that are essential for sustaining optimum efficiency. The complexity of reaching correct interleaving will increase because the sampling clock pace rises, requiring exact synchronization between ADCs to make sure superior spurious-free dynamic vary (SFDR) and efficient variety of bits (ENOB).

To deal with these challenges, this reference design leverages the noiseless aperture delay adjustment characteristic of the ADC12DJ5200RF gadget. This characteristic permits for 19 femtosecond (fs) section management steps, making the 20.8 GSPS interleaving possible by minimizing timing mismatches between ADCs. The design additionally incorporates a low-noise JESD204B clock generator, which makes use of the LMK04828 and LMX2594 units, making certain excessive system efficiency whereas assembly the 12-bit decision requirement. The reference design is provided with a number of key options, together with 20.8 GSPS time-interleaved, 12-bit, RF-sampling ADCs, a 6-GHz analog entrance finish, tremendous pattern clock section adjustment with 19 fs decision, and section synchronization of a number of ADCs. It additionally features a companion energy reference design, reaching over 85% effectivity with a 12-V enter, and helps JESD204B with as much as 32 lanes at knowledge charges as much as 12.8 Gbps per lane. 

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The design options an FMC+ connector, making it suitable with TI’s TSW14J57EVM seize card, which is good for high-speed knowledge acquisition methods. The time-interleaving method demonstrated right here addresses the important thing design challenges of lowering timing errors and optimizing system efficiency, notably by way of signal-to-noise ratio (SNR), SFDR, and ENOB. The {hardware} platform gives a versatile clocking resolution that allows designers to validate system efficiency with a spread of clocking supply choices. The onboard LMX2594 clock synthesizer provides glorious section noise traits at excessive frequencies, making certain dependable clocking for the ADCs. The ADC12DJ5200RF is a high-speed RF-sampling ADC able to immediately sampling enter frequencies from DC to over 10 GHz, with a sampling fee of as much as 5.2 GSPS in dual-channel mode and 10.4 GSPS in single-channel mode. 

The LMK0482x clock household gives the best efficiency clock conditioning with JESD204B assist, and the LMX2594 PLL synthesizer delivers a large frequency vary with out the necessity for an inner doubler, making it a perfect selection for this high-performance system. TI has examined this reference design. It comes with a invoice of supplies (BOM), schematics, meeting drawing, printed circuit board (PCB) structure, and extra. The corporate’s web site has extra knowledge concerning the reference design. To learn extra about this reference design, click on right here.