Analog-to-digital conversion based mostly on the traditional mixture of a voltage-to-frequency converter (VFC) with a counter has been round for (many) many years, primarily as a result of it has some sturdy time-proven benefits. VFC digitization is of course integrating, so excessive noise rejection is inherent, as is programmable decision (if you would like extra bits, simply depend longer). Sadly, excessive conversion velocity isn’t.
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Helpful decision (8 or extra bits) tens-of-microseconds VFC conversion instances require tens-of-megahertz output frequencies. There are current VFC designs that may flap that quick, e.g., Jim Williams’s superior 100 MHz King Kong and my very own “20 MHz VFC with take-back-half cost pump”. Nonetheless, these attainable options solely pose one other doubtlessly pesky downside. What to make use of for a counter?
Incessantly (no pun meant) the best and most cost-effective digital associate for a VFC is the µC’s onboard counter-timer peripheral (CTP), usually offering 16 bits of decision at zero added components value. Sadly, the need of taking a number of (e.g., 4) samples of every cycle of incoming pulses by onboard CTP logic limits most depend fee to a fraction (usually ¼) of the µC’s inner clock.
Thus, for a 20-MHz inner clock, 5 MHz is the quickest achievable CTP depend fee. Sorry, Kong.
After all, an exterior hardwired counter peripheral might be carried out that might simply accommodate quick VFCs (okay, possibly Kong not so completely straightforward), however value, components depend, and board space make this feature fairly unattractive.
Proven in Determine 1 is a compromise topology that mixes the CTP doing what it does greatest (offering plenty of bits), with a single exterior 4-bit MSI pre/scaler/accumulator chip. This extends the peripheral’s velocity by as much as 16x (therefore as much as 80 MHz with a CTP 5-MHz prime finish), at the price of (at most) 4 extra common objective I/O (GPIO) pins.
Right here’s the way it works.
Determine 1 100-MHz MSI counter prescales and accumulates VFC LSBs so clunky CTP can cope.
- 5 GPIO pins are programmed for interface with the preaccumulator:
- 4 as inputs (IN1 by means of IN4)
- One as output (OUT).
- IN4 can also be programmed for enter to the chosen CTP, which is programmed for 16-bit accumulation.
Every VFC integration cycle contains the next steps:
- OUT = 0 to disable counting.
- A 20-bit preliminary worth (X1) is fashioned by concatenating the states of the INx bits (as 4 LSBs) with the 16 bits of the CTP (as 16 MSBs), i.e., X1=[cccc cccc cccc cccc iiii].
- OUT = 1 for the specified integration interval. A sensible most = 220/VFCmax, shorter if decrease decision and/or increased conversion velocity is required.
- OUT = 0 to freeze counting.
- A 20-bit ultimate worth (X2) is fashioned by concatenating INx with the CTP.
- The 20-bit conversion end result = X2 – X1 modulo 220.
Be aware that if the ratio of max VFC output to max CTP depend fee is lower than 8x, then solely three INx pins want be allotted to the interface (Xx = [ccc cccc cccc ciii]), with IN3 programmed as CTP enter. If lower than 4x, then solely two, (Xx = [cc cccc cccc ccii]). And so forth.
If less complicated arithmetic is extra vital than conserving GPIO pins, then a sixth output pin will be related to 
and pulsed low on the onset of conversion to reset the INx bits to zero, together with the same preload of the CTP bits. This might eradicate steps #6 and #10 of the conversion sequence.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
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The publish Preaccumulator handles VFC outputs which are too quick for a unadorned CTP to swallow appeared first on EDN.
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