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World Unichip Corp. (GUC), the Superior ASIC Chief, introduced at this time that the GLink-3D interface (GUC’s Hyperlink for 3D die stacking) for the TSMC 3DFabric SoIC-X 3D stacking platform handed complete silicon testing, validating 3DIC interface hardening circulation. The primary GUC 3D buyer challenge additionally handed full silicon testing, validating a full spectrum of 3D implementation providers for AI/HPC/Networking purposes.
Typical AI/HPC/Networking chips mix giant reminiscence with high-performance logic. Logic good points energy, velocity and dimension enchancment when scaled to essentially the most superior course of whereas the SRAM scaling good points are reasonable. Stacking a logic chiplet at a extra superior course of node over an SRAM-dominant chiplet at an SRAM-scaling-efficient, much less superior node is essentially the most optimum value/efficiency answer. The high-bandwidth, low-latency, low-power GLink-3D interface IP is an enabler for this answer. Different challenges are thermal dissipation and energy distribution of 3D stacked chiplets. GUC developed a full 3D design circulation and carried out the primary buyer’s logic-over-memory 3D stacking product and it handed silicon validation. A silicon-correlated design and simulation circulation permit seamless implementation utilizing the rising UCIe-3D interface normal.
For the best 3D interface bandwidth density necessities, GUC developed the GLink-3D interface utilizing Double Knowledge Fee (DDR) and adaptive timing structure. The modular answer is versatile sufficient to assist customers’ buses and clocking schemes and to keep away from cross-die/nook timing closure challenges whereas offering 9 Tbps/mm2 bandwidth density. GLink-3D was validated utilizing TSMC’s first SoIC-X check chip with N5 CPU logic over N6 SRAM stacked dies. IP robustness was validated throughout a full vary of process-voltage-temperature corners, proving BER <1E-30, excessive provide voltage and frequency margins, and robust provide noise immunity. The following era GLink-3D for N2 to N7, concentrating on 20-40Tbps/mm2, 0.2ns-0.6ns latency and UCIe-3D compliant, can be underneath growth.
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“3D packaging strikes chiplet interface from die edge to essentially the most optimum location anyplace in a chiplet, making the shortest interconnect between logic and reminiscence,” stated Aditya Raina, CMO of GUC. “Along with CoWoS®, InFO, and SoIC design experience, package deal design, electrical and thermal simulations, and DFT and manufacturing testing, we offer our clients with a strong and complete answer, enabling quick design cycles and fast time-to-market of their AI/HPC/xPU/Networking merchandise.”
“3D expertise allows programs combining large processing energy and huge reminiscence, with every part created in essentially the most environment friendly course of node,” stated Igor Elkanovich, CTO of GUC. “We developed and silicon-validated 3D interface (GLink-3D) hardening service, 3D bodily implementation and timing closure, sign integrity, energy distribution and integrity, and SoIC thermal and mechanical simulations – a full package deal of providers permitting low-risk adoption of 3D expertise in our clients’ initiatives.”
Be taught Extra about GUC’s GLink IP with InFO/CoWoS Whole Answer
For extra info, please contact your GUC gross sales consultant straight or e mail [email protected].
CoWoS® is a registered trademark of Taiwan Semiconductor Manufacturing Co. in the US, Europe, China, Taiwan and/or different nations.
About GUC
World Unichip Corp. (GUC) is the Superior ASIC Chief that gives the semiconductor business with main IC implementation and SoC manufacturing providers, utilizing superior course of and packaging expertise. Primarily based in Hsinchu, Taiwan, GUC has developed a worldwide repute with a presence in China, Europe, Japan, Korea, North America and Vietnam. GUC is publicly traded on the Taiwan Inventory Change underneath the image 3443. For extra info, go to www.guc-asic.com.
