The mainstream adoption of 3D-IC has grow to be a query mark as a result of essential challenges starting from early-stage chip designs to 3D meeting exploration to closing design signoff. A brand new EDA instrument claims to deal with these points by integrating thermal evaluation instantly into all levels of the IC design circulation, spanning early evaluation to signoff evaluation, whereas providing multiple-use fashions.
At this 12 months’s Design Automation Convention (DAC) in San Francisco, California, Siemens EDA unveiled Calibre 3DThermal software program for thermal evaluation, verification, and debugging in 3D built-in circuits (3D-ICs). It allows chip designers to quickly mannequin, visualize, and mitigate thermal results of their designs from early-stage chip design to package-inward exploration to design signoff.
Determine 1 Calibre 3DThermal is a thermal evaluation answer primarily based on a whole understanding of the 3D-IC meeting. Supply: Siemens EDA
In all design flows, Calibre 3DThermal captures and analyzes thermal knowledge throughout all the design lifecycle. Siemens EDA has already joined forces with UMC to deploy a thermal evaluation circulation primarily based on Calibre 3DThermal.
What’s hampering 3D ICs
Semiconductor engineering groups specializing in designing and manufacturing bleeding edge, next-generation chips are turning to chiplets and 3D-IC architectures to combine extra performance into ever-shrinking footprints. Nonetheless, regardless of a number of speak, commercially out there semiconductors primarily based on 3D-IC architectures are nonetheless fairly exhausting to search out within the market.
Why? 3DIC architectures—which place a number of dies or chiplets subsequent to 1 one other and even stack dies vertically in a single package deal—current a variety of recent complexities and challenges as a result of larger numbers of energetic dies in shut proximity to one another or stacked vertically.
In different phrases, squeezing a number of energetic dies in such shut proximity—side-by-side or stacked vertically—in a single package deal comes with a number of recent and vexing challenges. These challenges—generally categorized as multi-physics—typically relate to controlling warmth dissipation since extreme warmth can impression the top gadget’s efficiency and reliability.
“There was a view that 3D IC goes to take over the world, however nobody goes to desert Moore’s Regulation transistor scaling,” stated Michael White, senior director of bodily verification product administration for Calibre design options at Siemens EDA. “Nonetheless, 3D IC shall be used for heterogeneous options in compute-intensive synthetic intelligence (AI) chips.”
At superior nodes like 2-nm, 3D IC is smart, he added. “Whether or not it’s utility processor, CPU or GPU, elements like I/O and HBM are going to be separate dies or separate chiplets, and it’s all going to be packaged in 2.5D or 3D IC.” Nonetheless, in these superior packages, controlling warmth dissipation turns into crucial.
Furthermore, design engineers can’t afford to attend till the meeting is full to determine and proper errors; it could actually severely disrupt design schedules.
“There’s a whole lot of warmth to be managed,” White stated. “In any other case, it could actually impression transistor habits on this new multi-physics area.” He additionally added that thermal impacts may couple with stress impacts coming from new supplies, how we stack, and putting of by silicon vias (TSVs) near energetic transistors.
Thermal evaluation to rescue
White makes the case for a shift-left strategy with Calibre bodily verification to assist designers do issues proper the primary time as an alternative of near tape-out. Whereas speaking to EDN earlier than the launch of Calibre3DThermal, he pointed to its key function, feasibility evaluation, which permits chip designers to begin the preliminary evaluation with minimal inputs. “As soon as extra data is on the market, it repeatedly refines the accuracy of the evaluation.”
Determine 2 The shift-left strategy allows chip designers to determine and resolve points early in design circulation with signoff-quality options. Supply: Siemens EDA
John Ferguson, senior director of DRC/3DIC product administration for Calibre design options, identified that chip designers spend years creating complicated 3D ICs, and after a thermal signoff, in the event that they discover an issue, there’s nothing they will do about it. “The concept of feasibility evaluation is to begin discovering potential issues early.”
Chip designers can later carry out extra detailed analyses contemplating metalization particulars and their impression on thermal concerns as extra detailed data turns into out there. This progressive strategy allows designers to refine their evaluation, apply fixes like floorplanning modifications, and add stacked vias or TSVs to keep away from thermal hotspots and dissipate warmth extra successfully.
The iterative course of continues till the ultimate meeting is full. Ferguson is fast to notice that Calibre3DThermal is a bit completely different than conventional thermal evaluation. “We have now a sooner means of performing thermal evaluation during which the Calibre half will work upfront to take a look at the die stage data, create correct fashions, and go that for creating fashions on the package deal stage.”
Calibre with multi-use fashions
Calibre 3DThermal—developed to deal with the challenges of 3D-IC architectures the place controlling warmth dissipation is a key requirement—presents quick and correct approaches to figuring out and quickly addressing complicated thermal points. It permits designers to iterate thermal evaluation at whichever design stage they’re engaged on.
Thermal evaluation at this superior stage requires a whole understanding of the 3D-IC meeting, so Calibre 3DThermal embeds a customized model of Siemens’ Simcenter Flotherm software program solver engine to create exact chiplet-level thermal fashions for static or dynamic simulation of full 3D-IC assemblies. Subsequent, debugging is streamlined by the standard Calibre RVE software program outcomes viewer.
It’s value noting that even while you put a identified good die (KGD) right into a package deal, you would possibly get warmth points.
“After getting extra dies, you may carry out extra mature thermal evaluation at a way more fine-grained stage,” Ferguson stated. “Once you carry all dies into the package deal, that’s while you add further accuracy after which take a look at selective chiplets or selective IPs in these chiplets.”
Now that chip designers have data on the dies and package deal ranges, this data could be handed upstream to the board stage and even to the big system stage, like a jet engine design.
Associated Content material
- A thermal-aware IC design methodology
- The Significance of 3D IC Ecosystem Collaboration
- Reliability challenges in 3D IC semiconductor design
- How the Worlds of Chiplets and Packaging Intertwine
- Heterogeneous Integration and the Evolution of IC Packaging
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The submit Thermal evaluation instrument goals to reinvigorate 3D-IC design appeared first on EDN.
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