Nvidia’s CEO Jensen Huang has made waves by saying that his firm’s most superior synthetic intelligence (AI) chip, Blackwell, will transition from CowoS-S to CoWoS-L superior packaging know-how. That additionally reveals how TSMC’s superior packaging know-how—chip on wafer on substrate (CoWoS)—is evolving to beat interconnect battles inside massive, highly effective chips for AI and different high-performance computing (HPC) purposes.
The CoWoS-S superior packaging know-how makes use of a single silicon interposer and through-silicon vias (TSVs) to facilitate the direct transmission of high-speed electrical indicators between the die and the substrate. Nevertheless, single silicon interposers usually confront yield points.
However, CoWoS-L, TSMC’s newest packaging know-how, makes use of an area silicon interconnect (LSI) together with an RDL interposer to kind a reconstituted interposer (RI) to reinforce chip design and packaging flexibility. It additionally preserves the engaging function of CoWoS-S within the type of TSVs whereas mitigating the yield points arising from the usage of massive silicon interposers in CoWoS-S.
In response to Reuters, Nvidia is promoting its Blackwell chips as shortly as TSMC can manufacture them, however packaging has turn into a bottleneck as a result of capability constraints. That’s startling as a result of, as Huang famous, the quantity of superior packaging capability at TSMC might be 4 instances the quantity obtainable lower than two years in the past.
Determine 1 CoWoS-L marks a big development over CoWoS-S by way of efficiency and effectivity for AI and HPC purposes. Supply: TSMC
Huang additionally instructed Taiwanese reporters that Nvidia continues to be producing Blackwell’s predecessor, Hopper, utilizing TSMC’s CoWoS-S superior packaging know-how. “It’s not about lowering capability. It’s really rising capability into CoWoS-L.”
Superior packaging in flux
Nvidia’s foray into new know-how is a stark reminder of how shortly superior packaging wants are altering. Apparently, the semiconductor business is eying a brand new set of superior packaging constructing blocks to dramatically improve the bandwidth and interconnect density of AI chips.
TSMC’s CoWoS is a 2.5D semiconductor packaging know-how that will increase the variety of I/O factors whereas lowering interconnect size between logic and reminiscence elements. Nevertheless, rising HPC workloads, notably these associated to AI coaching, demand even increased reminiscence bandwidth as a result of frequent reminiscence accesses.
CoWoS-L can stack as much as 12 HBM3 units at a decrease price than CoWoS-S and thus has the potential to turn into the mainstream CoWoS know-how for future AI chips. Past CoWoS-L, TSMC is warming as much as co-packaged optics (CPO), which replaces conventional electrical sign transmission with optical communications.
Determine 2 TSMC has made vital progress in its silicon photonics technique by integrating CPO with superior semiconductor packaging. Supply: TrendForce
The present AI chips use copper interconnects, which more and more face bottlenecks as bandwidths widen. In CPO, optical interconnect indicators can obtain increased bandwidth than their electrical counterparts. For example, CPO helps as much as 1.6 Tbps bandwidth, which is 1.8 instances wider than Gen 4 NVLink interconnect utilized by Nvidia in its present GPUs. Furthermore, energy consumption can be as much as 50% decrease.
In response to Taiwanese media outlet UDN, TSMC has accomplished the event of CPO, and it plans to supply CPO samples to 2 of its main clients, Broadcom and Nvidia, later this yr. Moreover, UDN studies that TSMC plans to scale up the manufacturing of CPO in 2026.
AI chips constituting excessive logic-to-logic and logic-to-memory bandwidth are driving improvements within the superior packaging realm. The transfer from CoWoS-S to CoWoS-L and the introduction of CPO are harbinger of this pivot within the semiconductor business ecosystem, which is now more and more pushed by AI purposes.
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The submit Nvidia, TSMC, and superior packaging realignment in 2025 appeared first on EDN.
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