A brand new UCIe IP working at as much as 40 Gbps permits extra information to journey effectively throughout heterogeneous and homogeneous dies—chiplets—in immediately’s synthetic intelligence (AI)-centric information middle techniques. It helps natural substrates in addition to high-density superior packaging applied sciences, permitting designers to discover the packaging choices that finest match their necessities.
The 40 G UCIe IP answer from Synopsys consists of PHY, controller, and verification IP, which makes it an entire protocol stack. The PHY with a controller on prime facilitates a seamless connection between two dies through on-chip interconnect protocols—together with AXI, CHI C2C, CXS, PCIe, CXL, and streaming—to permit a die-to-die connection between materials. Verification IP comes with Synopsys 3DIC Compiler and all of the required design collateral and documentation for automated routing move, interposer research, and sign integrity evaluation.
The 40G UCIe IP is constructed on a silicon-proven structure with interoperability to a number of foundry processes. Supply: Synopsys
Synopsys claims its 40G UCIe IP helps 25% extra bandwidth than the UCIe specification, enabling 12.9 Tbps/mm of knowledge to journey between heterogeneous and homogeneous dies with out impacting vitality effectivity and silicon footprint. In different phrases, whereas complying with the newest UCIe 2.0 specification, the IP answer exceeds the usual with further bandwidth effectivity.
“Heterogeneous integration with high-bandwidth die-to-die connectivity provides us the chance to ship new reminiscence chiplets with the effectivity wanted for data-intensive AI purposes,” stated Jongwoo Lee, VP of system LSI IP growth crew at Samsung Electronics.
Key design options
The 40 G UCIe IP, whereas supporting each UCIe 1.1 and UCIe 2.0 requirements, affords further capabilities for designers to simply combine die-to-die connectivity IP and simplify general chiplet design. Begin with a single clock reference that helps 100-MHz reference clocking for all UCIe PHYs, eliminating the necessity for added high-frequency system PLLs.
The inner PLL generates all of the high-speed peripheral clock (pclk) and decrease native clock (lclk) frequencies wanted throughout initialization and common operation. Furthermore, the decrease native clock is shared with the controller to additional simplify system integration. These capabilities simplify clocking structure, optimize energy, and pace up die-to-die hyperlink initialization without having to load firmware.
Subsequent, sign integrity displays (SIMs) are built-in into the IP for prognosis and evaluation to make sure multi-die package deal reliability and high quality. These take a look at options embedded within the PHY permit high-coverage assessments of the PHY on the wafer stage for recognized good die (KGD) and after package deal meeting. Automotive chiplet designers can leverage the built-in SIM sensors and take a look at and restore capabilities to construct extra dependable dies whereas addressing the demanding automotive necessities.
Then there are vendor-defined messages that allow using present UCIe sideband channels to ship low-speed, low-priority communication between dies with out hampering the primary information path. So, as an alternative of interrupting the high-bandwidth path with one of these site visitors, a die can use the UCIe sideband to ship instructions corresponding to interrupts and telemetry to the opposite die.
Lastly, hardware-based bring-up speeds initialization without having to load heavy firmware on the distant chiplet. In any other case, when a UCIe hyperlink bring-up makes use of heavy firmware to be loaded into the die, a separate path can be required to load the firmware. That’s wasteful and time consuming from a design standpoint.
Such capabilities and better speeds bode nicely for the UCIe interconnect, a de facto normal for die-to-die connectivity. The assist for superior packaging may make chiplets growth extra inexpensive.
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The put up New UCIe IP raises the chiplet bandwidth bar to 40 Gbps appeared first on EDN.
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