A latest design concept, “Destructive time-constant and PWM program a flexible ADC entrance finish,” provided a reasonably peculiar ADC entrance finish (see Determine 1). It includes a programmable achieve (PG) instrumentation amplifier (INA). It makes use of PWM management of a flying capacitor to implement a 110-dB CMRR, excessive impedance differential enter and destructive time-constant exponential amplification with greater than 100 discrete programmable achieve steps. It’s then topped off with a built-in pattern and maintain (S&H). Therefore PGINASH. Catchy. Ahem.
Determine 1 PGINASH: An unconventional ADC entrance finish with INA inputs, programmable achieve, and pattern and maintain.
Wow the engineering world along with your distinctive design: Design Concepts Submission Information
Because of A1c’s achieve of (R3 / R2 + 1) = 2, through the PWM = 1 achieve accumulation section the connection established from U1c’s output by way of U2a and R1 to C creates optimistic suggestions that makes the voltage captured on C multiply exponentially with a (destructive) time-constant Tc of (nominally):
Tc = R1*(C + Cstray) =
= 14.3k*(0.001µF + (8pF (from U2a) + 1pF (from U1c)))
= 14.3k*1009pF = 14.43µs
= 10µs / ln(2)
G = achieve increment of two0.1 = 1.0718 = 0.6021dB per us of accumulation time T
G10 = 2.0 = 6.021dB per 10µs of T
This combines with A1c’s fastened achieve of two to complete
Nominal internet Achieve = 2GT/10µs
In fact, the key phrase right here is “nominally.” Each R1 and C can have nonzero tolerances, maybe as poor as ±1%, and ditto for R2 and R3. Furthermore, additional time-constant, and subsequently achieve, error can come up from U2 swap to modify ON resistance mismatches. The web unhealthy information, pessimistically assuming worst case mutual error reinforcement of all of the time-constant part tolerances, is A1c’s achieve might range by ±2% and G by as a lot as ±3%. That is removed from satisfactory for precision information acquisition! What to do?
The next sequence is usually recommended as a easy software-based in-circuit calibration methodology utilizing a related ADC and requiring simply two calibration voltages to be manually related to the IA inputs as calibration progresses, to fight the assorted causes of front-end error.
GAIN ERROR
The primary calibration voltage (Vcal) is used to explicitly measure the as-built achieve elements. Right here’s the way it works:
Vcal = Vfs/Vheadroom
the place
Vfs = ADC full-scale Vin
Vheadroom = (2*1.02)*(2*1.04)2 = 8.8
e.g., if Vfs = 5v, Vcal = 0.57v
Vcal’s absolute accuracy isn’t significantly necessary, +/-1% is lots satisfactory. Nevertheless it ought to be steady to higher than 1 lsb through the calibration course of. Join Vcal to the INA inputs, then take two ADC conversions: D1 with achieve accumulation time T =10 µs and D2 with T = 20 µs. Thus, if 2x = the as-built A1c achieve and G = the as-built exponential achieve, the ADC will learn:
D1 = ADC(2x *G10*Vcal)
D2 = ADC(2x*G10*G10*Vcal)
Averaging a quantity (maybe 16) acquisitions of every worth might be a good suggestion for greatest accuracy. The following step is a few arithmetic:
D2/D1 = (2x*G10*G10*Vcal)/(2x*G10*Vcal) = G10
D1/ (G10*Vcal) = (2x*G10*Vcal)/(G10*Vcal) = 2x
G = (G10)0.1
That wasn’t so unhealthy, was it? Now we if we wish to set (most) any desired conversion achieve of Y, we simply have to compute a achieve accumulation interval of:
T(µs) = log(Y/2x)/log(G)
Be aware if that this math yields T < 1 µs, we’ll have to bump Y for some additional time (and achieve) to permit for capacitor “flight” and sign acquisition.
INPUT OFFSET ERROR
There may be, nevertheless, one other error supply we haven’t lined: U1 enter offsets. Though the TLV9164 typical offset is simply 200 µV, max can vary as excessive as 1.2 mV. If uncorrected, the three enter amplifiers’ offsets may sum to three.6 mV. This is able to render the higher achieve vary of our amplifier of little worth. To repair it, we want one other enter voltage reference (Vzero), some extra arithmetic, and one other ADC conversion to measure the Voff offset and permit software program subtraction. We’ll use plenty of achieve to get loads of decision. Vzero ought to ideally be correct and steady to <10 µV to take full benefit of the 9164’s wonderful 0.25 µV/oC drift spec’.
Let Vzero = 4.00mV
N = log(Vfs/(.008v * 2x))/log(G)
D3 = ADC(2x*GN*(Vzero + Voff))
Voff = D3/(2x*GN) – Vzero
And there you could have it. To precisely therapeutic massage any uncooked ADC consequence into the precise Vin enter that produced it, write:
Vin = (ADC(Vin)/(2x GN)) – Voff
However keep away from GN > Vfs /(2x*Voff). In any other case A1c and the ADC could also be pushed into saturation by amplified offset. Additionally, issues might (okay, will) get noisy.
Okay. However what about…
LEAKAGE CURRENT ERROR
The leakage present conundrum comes from the truth that destructive time-constant present from U1c by way of R1 isn’t the one supply of gain-phase cost for C. Sadly, leakage currents from U2’s X pin and U1’s noninverting enter additionally contribute a mischievous share. U1’s contribution is a negligible 10 pA or so, however U2’s could be giant sufficient to develop into problematic.
The burning query is: How a lot do HC4053 switches actually leak? Reeeeeally? Datasheets are of surprisingly little assist, with the reply seeming to vary over actually a million-to-one, pA to µA, vary.
Determine 2 quantifies the consequence for some believable 100 pA to 1 µA numbers.
Determine 2 The enter referred present – equal voltage offsets.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a great distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
- Destructive time-constant and PWM program a flexible ADC entrance finish
- Simulating the front-end of your ADC
- Parsing PWM (DAC) efficiency: Half 1—Mitigating errors
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The put up In-situ software program calibration of the flying capacitor PGINASH appeared first on EDN.
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