ASML Goals for Hyper-NA EUV, Shrinking Chip Limits

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ASML has once more introduced plans for a brand new lithography device that may prolong design limits for the very best transistor-density chips.

The corporate’s former president, Martin van den Brink, stunned consultants with the announcement of the brand new “Hyper-NA” EUV know-how that’s nonetheless within the early phases of growth, in keeping with world R&D group imec, which has labored carefully with ASML. Hyper NA would comply with the Excessive-NA programs that ASML put in early this 12 months for the primary time at an Intel semiconductor facility within the U.S. state of Oregon.

“Transferring ahead long run, we have to enhance our illumination system, and we’ve got to go to Hyper-NA,” van der Brink stated in a Might presentation at imec’s ITF World in Antwerp. “In parallel, we’ve got to drive the productiveness on all of our programs to 400 to 500 wafers per hour.”

Excessive-NA takes numerical aperture (NA) to 0.55 NA from the 0.33 NA of earlier EUV instruments. About three years in the past, the corporate stated Excessive-NA would assist chipmakers attain course of nodes effectively past 2 nm for at the very least 10 years. Now, ASML has stated that round 2030, the corporate will provide Hyper-NA, reaching 0.75 NA, in keeping with a picture van den Brink confirmed on the imec occasion.

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It was the primary time that ASML added Hyper NA EUV to their roadmap, in keeping with Imec Superior Patterning Program Director Kurt Ronse, who has developed lithography in cooperation with ASML for greater than 30 years.

“There’s quite a lot of analysis on going now,” he instructed EE Instances. “Can we go increased than 0.55 to 0.75, 0.85? Hyper-NA actually brings some new challenges.”

One of many issues is gentle polarization beginning round 0.55 NA, in keeping with Ronse.

“When you go increased than 0.55, in a short time you see that polarization is killing your distinction, as a result of one of many polarization orientations is mainly canceling out the sunshine,” he stated. “You would wish polarizers to be able to keep away from that.” The draw back is that polarizers block gentle, cut back energy effectivity and improve manufacturing value, he famous.

ASML is the world’s solely firm that makes the EUV instruments which are indispensable for making chips with the very best transistor densities. Chip designers like Nvidia, Apple and AMD depend on the EUV instruments at main foundry Taiwan Semiconductor Manufacturing Co. (TSMC) to make processors utilized in AI {hardware} and different high-performance computing tools.

Two years in the past, imec began engaged on Hyper-NA with pc simulations.

“Step by step you noticed that increasingly more corporations began to be eager about Hyper-NA and began their very own research,” Ronse stated. “Zeiss have been beginning to make their lens designs, and steadily additionally ASML was changing into extra open on Hyper-NA, however they by no means have put it on the roadmap earlier than, so far as I do know. It was at all times ending with 0.55 NA.”

One other problem of Hyper-NA would be the resist.

“Already at 0.55 NA we could have skinny down the resists,” Ronse stated. “With Hyper-NA, it even will get worse. This can lead to extra challenges for etch selectivity”.

Excessive-NA simply beginning

In April, Intel Foundry put in the trade’s first Excessive-NA lithography system. Intel stated the brand new device supplies the flexibility to dramatically enhance decision and have scaling for the subsequent era of processors, enabling course of management past Intel’s 18A course of node that’s roughly equal to TSMC’s upcoming 2-nm course of. TSMC doesn’t plan to put in Excessive-NA instruments at this level.

“TSMC doesn’t want Excessive-NA but,” Ronse stated. “Towards the top of this decade, they’ll probably introduce it.”

At current, TSMC can use its experience in double-patterning along with its current EUV instruments, Ronse added.

“What is actually essential in double patterning is the edge-placement error,” he stated. “Your two masks need to be completely aligned. Intel desires to keep away from that. The massive distinction with Intel is that they haven’t mastered double patterning in addition to TSMC. Consequently, they like the next decision with Excessive-NA EUV.”

Different main chipmakers that use EUV, akin to Samsung, Micron and SK Hynix, are additionally contemplating Excessive-NA.

Excessive-NA ought to final by means of course of nodes going from 2 nm to 14 angstroms, 10 angstroms and maybe even 7 angstroms, in keeping with Ronse. After that, Hyper-NA will begin to take over, he added.

Hyper-NA will cut back the “harmful development” of double patterning, van den Brink stated in his presentation.

“When you do double patterning, you must do the whole lot twice. That simply turns into dearer,” Ronse stated.

After Excessive-NA

There are few options to Hyper-NA as soon as Excessive-NA runs out of steam, Ronse says.

Folks have thought-about nanoimprint in its place, however the throughput is often far beneath that of a Excessive-NA scanner. There’s additionally the thought of multi-beam electron-beam lithography, which eliminates using costly photomasks by writing patterns on to a silicon wafer. The one firm that developed e-beam lithography instruments, Netherlands-based Mapper, has gone out of enterprise.

Exterior of lithography, researchers have tried to shrink the scale of transistors to proceed scaling downward, however that strategy can also be reaching bodily limits.

“You can’t think about that there’s going to be units of solely 2 angstroms,” Ronse says. “It’s solely two atoms. In some unspecified time in the future, it has to cease.”

New supplies will probably take the place of silicon, in keeping with Ronse.

“There are new supplies which have the next mobility for electrons,” Ronse stated. “These are far more troublesome to placed on the wafer. Analysis teams are engaged on that.”

The wafers will keep silicon, Ronse notes.

“It’s just for a number of ranges that you’ll have to deposit a really skinny layer the place the electrons need to undergo. What shall be wanted is devoted tools that may uniformly deposit that over an entire wafer. Proper now, it’s within the labs. It’s solely on small areas one is engaged on. There shall be new deposition instruments. Additionally, etching these supplies could also be harder, so we want new etching strategies. The premise of the chip will nonetheless be silicon.”