Adverse time-constant and PWM program a flexible ADC entrance finish

A wide range of analog front-end features sometimes help ADCs to do their jobs. These embrace instrumentation amplifiers (INA), digitally programmable acquire (DPG), and pattern and holds (S&H). The circuit in Determine 1 is a bit atypical in merging all three of those features right into a single topology managed by the timing from a single (PWM) logic sign.

Determine 1 Two generic chips and 5 passives make a flexible and unconventional ADC entrance finish

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

Determine 1’s differential INA fashion enter begins off conventionally, consisting of tera-ohm impedance and picoamp bias CMOS followers U1a and U1b. The 916x household op-amps are fairly good RRIO gadgets for this job, with sub-mV enter offset, 110 dB CMR, 11 MHz gain-bandwidth, 33 V/µs slew price, and sub-microsecond setting time. They’re additionally cheap. Turning this right into a excessive CMR differential enter, nevertheless, is the place the circuit begins to get unconventional. The ploy in play is the “flying capacitor”. 

Through the logic-0 interval of the PWM, by way of switches U2a and U2b each ends of capacitor C are pushed by the unity-gain follower amplifiers with CMR restricted solely by the amplifier’s 110 dB = 300,000:1. In contrast to a typical precision differential INA enter, no vital resistor matching is concerned. A minimal length interval of a microsecond or two is sufficient to precisely seize and settle to the enter sign. When the PWM enter transitions to logic-1, one finish of C is grounded (by way of U2b) whereas the opposite turns into the now single-ended enter to U1c (by way of U2a). Then issues get even much less standard.

The connection established from U1c’s output to C by way of U1c and R1 creates constructive suggestions that causes the voltage captured on C to multiply exponentially with a (damaging) time-constant of:

Tc = (R1 + (U2 on resistance)) C
= (14.3 kΩ + 130) 0.001 µF = 14.43 µs
= 10 µs / ln(2)

Resulting from A1c’s acquire = R3 / R2 + 1 = 2 the present by way of R1 from Vc:

I_R1 = (Vc – 2Vc) / R1
= Vc / -R1

Thus, R1 is made successfully damaging which makes R1C damaging and for any time T after the 0-1 transition of PWM the acquainted exponential decay of:

V(T) = V(0) e^-(T/RC)

turns into with a damaging R1:

= V(0) e^-(T/-R1C) = Vc(0) e^{– -(T / 14.43 µs)} = Vc(0) e^{(T / 14.43 µs)}
= Vc(0) 2^{(T / 10 µs )}

Subsequently, taking U1c’s acquire of two.00:

Vout = Vc(0) 2^{((T / 10 µs) + 1)}

For instance, if a 7-bit 1 MHz PWM is used, then every 1µs increment within the length of the logic-1 interval will equate to a acquire increment of 2^0.1 = 1.072 = 0.60 dB.  So, a 100 PWM 1-count would create a acquire of 2^{((T / 10 µs) + 1)}  = 66.2 dB = 2048. Having 100 out there programmable acquire settings is a helpful and strange characteristic.

 Notice that R1 and C needs to be precision with low-tempco varieties like steel movie and C0G in order that the acquire/time relationship will probably be correct and secure. The 14.43 µs = 11 kHz roll-off of R1C interacts with the 11 MHz acquire bandwidth of U1c to supply ~60 dB of closed loop acquire. That is sufficient for 10-bit acquisition accuracy.

Throughout this PWM = 1 exponential acquire part, the U2c change causes the output capacitor and U1d to trace Vc, which is captured and held for enter to the related ADC in the course of the subsequent PWM = 0 part. Whereas the entrance finish of the circuit is buying the following pattern.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.

 Associated Content material

• Simulating the front-end of your ADC
• DPGA situations alerts with damaging time fixed
• Parsing PWM (DAC) efficiency: Half 1—Mitigating errors
• PWM DAC settles in a single interval of the heart beat practice

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