Dynamic random-access reminiscence (DRAM) chips comprise many different transistors in addition to the entry transistor to allow full operation of the DRAM reminiscence. These peripheral transistors should meet stringent necessities which preclude a ‘copy-paste’ of normal logic transistor course of flows.
One essential requirement imposed by current DRAM chip architectures is the flexibility of the periphery to resist thermal therapies at 550-600°C and above. Whereas the first half of this text collection targeted on DRAM fundamentals and peripheral circuits, this half will present an in depth account of DRAM periphery, explaining totally different generations of thermally steady peripheral transistor expertise starting from planar high-k/metal-gate transistors to FinFETs.
DRAM periphery: From SiON-based gate stacks to high-k/metallic gates
Till 2018, DRAM peripheral transistors have been predominantly made in planar logic MOSFET expertise with poly-Si/SiO2 or poly-Si/SiON gates. These applied sciences have been much less superior than the transistors used for high-performance logic as a way to keep the DRAM cost-per-bit trendline.
Nonetheless, an improved expertise for the periphery turned essential to preserve tempo with the efficiency enhancement enabled by subsequent generations of DRAM reminiscence. The obvious candidate was transferring to a planar transistor structure with a high-k/metal-gate stack—a transition that occurred as early as 2007 within the high-volume manufacturing of logic applied sciences.
Since about 2007, imec, along with its companions, has actively explored a DRAM-compatible model of high-k/metal-gate transistors and proposed a number of materials and integration choices to the reminiscence {industry}. At the moment, virtually each system with a DRAM reminiscence inside incorporates a planar peripheral transistor expertise with high-k/metallic gates, which imec has been pioneering for greater than 15 years.
Under is a grasp of among the proposed materials, module, and integration choices, all differing in fabrication complexity and efficiency ranges.
Excessive-k/metal-gate integration: Thermally steady gate-first and gate-last integration flows
One of many options demonstrated by imec for potential early introduction was primarily based on a gate-first integration strategy, by which the metallic gate is deposited earlier than the high-temperature supply/drain junction activation anneal. Gate stacks for nMOS and pMOS could be optimized individually through the use of totally different work operate metals and layer thicknesses for the high-k/metal-gate stack (for instance, TiN/Mg/TiN for n; TiN for p).
One of many essential parameters is acquiring an efficient work operate that’s low sufficient for nMOS and excessive sufficient for pMOS to make sure Ion/Ioff ratio. Researchers achieved this by doping the gate stacks (with totally different dopants for pMOS and nMOS), which enabled a shift within the threshold voltages.
The selection of the dopant supplies and their integration additionally offered a knob for bettering the thermal stability of the gate stack and enabling the totally different Vth required by the DRAM chip. The DRAM-specific requirement for low gate leakage was addressed, amongst others, by adopting thicker gate stacks in comparison with logic-oriented options.
Determine 1 Sketch of the essential fabrication steps is proven in a gate-first integration strategy for planar high-k/metal-gate peripheral transistors. Supply: PSS
Imec additionally efficiently demonstrated a thermally improved model of a gate-last integration strategy, additionally referred to as substitute metallic gate (RMG) circulation. In a gate-last circulation, a poly-Si capped dummy gate is deposited and stays in place till the junction activation anneal is utilized. After that, the dummy poly is changed by the goal metallic gate.
Optimized supply/drain junctions
Supply/drain junctions are essential to make sure the performance of MOSFET transistors. They’re shaped by making a dopant gradient within the supply/drain areas. As conduction channel lengths continued to shrink, ultra-shallow junctions turned indispensable to make sure good electrostatic management over the channel. Nonetheless, for peripheral transistors, the thermal therapies throughout DRAM reminiscence anneal set off an undesirable diffusion of the dopants, requiring extra advanced course of flows to keep up the dopant gradient.
This situation could be addressed by altering the junction implant scheme utilizing, for instance, pre-amorphization implants and junction co-implants. Imec demonstrated a number of units of optimized junctions suited to numerous threshold voltage targets.
A thermally steady silicide course of
A basic problem for all transistors is to maintain the supply/drain contact resistance as little as attainable. Supply/drain contacts are shaped by bringing a metallic in touch with the supply/drain areas, making a Schottky barrier on the interface.
To make sure low resistance, two methods are usually utilized: (1) heavy doping of the supply/drain areas and (2) full silicidation of the supply/drain areas—the silicides being shaped by way of the response of the contact metallic with the doped Si.
Nonetheless, Ni(Pt) silicide, historically utilized in logic units, can’t face up to the DRAM-related anneal temperatures. Imec proposed a thermally steady NiPt-based silicide module with low contact resistance by implementing further implants and annealing steps for silicide stabilization.
Thermally steady, FinFET-based peripheral platform
Purposes like automotive, synthetic intelligence (AI) and machine studying (ML) impose more and more stringent necessities on DRAM reminiscences, driving the necessity for sooner, extra dependable and energy environment friendly peripheral transistors. One choice is to retrace the trail of ‘logic’ and transfer from planar high-k/metal-gate transistors to FinFETs.
The logic roadmap made this transition as early as 2011 after R&D clearly confirmed the superior efficiency of transistors with fin-shaped conduction channels: improved Ion/Ioff, higher quick channel management, greater drive present at decreased footprint (because of the next efficient width of the channel), and decrease energy consumption—whereas holding value below management. On prime of that, using tall fins offers a solution to cut back the brink voltage mismatch, which may significantly profit the DRAM sense amplifiers.
Identical to for the planar variations, the DRAM-specific necessities preclude a copy-paste of FinFET course of flows developed for normal logic. In response, imec developed a thermally steady FinFET-based peripheral expertise platform with built-in modules optimized for DRAM. A number of flavors with totally different performance-cost trade-offs have been proposed to the {industry} for his or her next-generation DRAM merchandise.
Thermally steady gate-first and gate-last FinFET integration flows
In 2021, imec reported the primary experimental demonstration of a thermally sturdy integration circulation for FinFETs utilizing an optimized gate-first strategy for implementing the high-k/metal-gate stack. In comparison with a conventional gate-first strategy, the modified circulation implements gate stacks with the identical thickness and the identical work operate metallic for each nMOS and pMOS. So-called Vth shifter supplies are then subtle into the high-k dielectric to tune the efficient work operate of the nMOS and pMOS units.
This modified gate-first strategy reduces the gate asymmetry and enhances the thermal stability of the circulation. By utilizing this circulation, the researchers demonstrated improved Ion/Ioff and quick channel management over planar high-k/metal-gate counterparts. These metrics didn’t degrade after the DRAM-specific anneal. Flavors with taller fins (with as much as 80-nm peak) have additionally been developed, with improved threshold voltage mismatch and space acquire.
Determine 2 Instance of a fabricated high-k/metal-gate fin shows transmission electron microscope (TEM) cross sections for 40-nm, 65-nm, and ~80-nm tall fins. Supply: imec
A disadvantage of the gate-first integration strategy is the comparatively excessive threshold voltage, which originates from the affect of the high-temperature anneal on the gate stack throughout junction activation. This situation could be solved utilizing a gate-last (or RMG) integration strategy, which, nevertheless, comes with further course of steps. At IEDM in 2022, imec confirmed a thermally steady model of a FinFET gate-last circulation.
Determine 3 The above picture reveals a number of related course of step for the proposed gate-last course of circulation for thermally steady FinFETs. Supply: 10.1109/IEDM45625.2022.10019422
An optimized and thermally steady gate-last FinFET circulation with a Mo-based work operate metallic for pMOS
Typical for a gate-last circulation is using totally different work operate metals for nMOS and pMOS units. At VLSI in 2024, imec demonstrated the efficiency advantages of utilizing a novel Mo-based work operate metallic for pMOS as a substitute of the traditional TiN-based strategy. The brand new gate stack module was efficiently built-in right into a gate-last FinFET circulation and confirmed to be thermally steady.
The DRAM-compatible circulation with built-in Mo-based p-work operate metallic yielded sufficiently low Ioff present and low threshold voltage (0.12 V) for the pMOS units. The FinFETs have been additionally benchmarked towards a thermally steady planar high-k/metal-gate reference, exhibiting a thrice greater Ion (at goal Ioff) for a similar Si footprint. These outcomes make the thermally steady gate-last FinFET circulation a precious candidate for sub-10 nm DRAM peripheral logic.
Determine 4 On left and center are TEM photographs throughout fins on a hoop oscillator and on proper is elemental mapping throughout gate (EDS) exhibiting CMOS patterning and first rate conformality of the Mo-based p-work operate metallic stacks. Supply: VLSI 2024
Thermally steady Nb-based metallic contacts with low contact resistance
In earlier work on planar high-k/metal-gate primarily based peripheral transistors, imec researchers lowered the supply/drain contact resistance by bettering the dopant profile and including pre-amorphization implants. At IEDM in 2024, imec launched a unique strategy: changing the traditional Ti contact metallic with Nb for pMOS units.
The thermal stability of the Nb-based contact module was demonstrated for the primary time. As well as, superior efficiency was noticed when built-in into the gate-last FinFET platform: document low contact resistance, decreased total parasitic resistance, and improved Ion.
Determine 5 The above chart reveals a comparability of the contact resistivities of Ti- and Nb-based contact modules (totally different thicknesses) for earlier than and after DRAM anneal. Supply: IEDM 2024
Forward of DRAM mass manufacturing
Imec pioneered peripheral transistor expertise 10 years forward of the {industry}’s mass manufacturing introduction. In its most up-to-date R&D work, imec demonstrated an industry-relevant, thermally steady FinFET-based platform to fulfill the necessities for sub-10 nm DRAM. A number of flavors have been developed as attainable options for next-generation DRAM merchandise, offering totally different ranges of fabrication complexity and transistor efficiency.
Extra disruptive ideas are envisioned in the long term to proceed the DRAM scaling path. Certainly one of these is constructing the periphery on a separate wafer and integrating it with the reminiscence array utilizing superior wafer bonding methods. Though this strategy comes with further course of steps, a real profit is the relaxed requirement for thermal stability, because the periphery is now manufactured individually from the reminiscence array.
Imec lately initiated R&D work on peripheral transistors for this new DRAM structure, guided by insights obtained from planar and FinFET-based expertise.
Alessio Spessot, technical account director, has been concerned in growing superior CMOS, DRAM, NAND, rising reminiscence array, and periphery throughout his stints at Micron, Numonyx, and STMicro.
Naoto Horiguchi, director of CMOS system expertise at imec, has labored in Fujitsu and the College of California Santa Barbara whereas being concerned in superior CMOS system R&D.
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