SoC interconnect automates processes, reduces wire size

A brand new network-on-chip (NoC) IP goals to dramatically speed up chip growth by introducing synthetic intelligence (AI)-driven automation and lowering wire size to decrease energy use in system-on-chip (SoC) interconnect design. Arteris, which calls its newly launched FlexGen interconnect IP a sensible NoC, claims to ship a 10x productiveness enhance, shortening design iterations from weeks to days.

Trendy chips—related by billions of wires—are ever-expanding with rising complexity. Trendy SoCs have 5 to twenty+ distinctive NoC situations, and every occasion can require 5-10 iterations. In consequence, SoC design complexity has surpassed guide human capabilities, which requires smarter NoC automation.

“In SoC interconnect, whereas know-how has superior to new ranges, quite a lot of work remains to be carried out in guide mode,” stated Michal Siwinski, CMO of Arteris. FlexGen accelerates chip design by shortening and lowering iterations from weeks to days for better effectivity.

“Whereas FlexGen remains to be utilizing the tried-and-tested NoC IP know-how as primary constructing blocks, it automates the present infrastructure by using AI know-how,” stated Andy Nightingale, VP of product administration and advertising at Arteris. “With FlexGen, we automate the NoC IP era to scale back the guide work whereas opening high-quality configurations that rival or surpass the guide designs.”

Determine 1 A FlexNoC guide interconnect (above) is proven for an ADAS chip, whereas an automatic FlexGen interconnect (blow) accelerates this chip design by as much as 10x. Supply: Arteris

In accordance with Nightingale, it enhances engineering effectivity by 3x whereas delivering expert-quality outcomes with optimized routing and lowered congestion. Dream Chip Applied sciences, a provider of superior driver help techniques (ADAS) silicon options, acknowledges lowering design iterations from weeks to days whereas utilizing FlexGen in its Zukimo 1.1 automotive ADAS chip design.

“FlexGen’s automated NoC IP era permits us to create floorplan adaptive topologies with advanced automotive site visitors necessities inside minutes,” stated Jens Benndorf, GM at Dream Chip Applied sciences. “That enabled speedy experimentation to search out design candy spots and to reply shortly to floorplan adjustments with virtually push-button timing closure.”

Shorter wire size

With AI comes a compute efficiency explosion, and in consequence, the complexity of interconnects goes to exponential ranges in SoC designs, resulting in an enormous explosion within the variety of wires. FlexGen claims to scale back wire size by as much as 30% to enhance chip or chiplet energy effectivity.

“We’re additionally tackling the massive downside of wire size in fashionable SoC designs,” stated Nightingale. “Because the gate depend dimension reduces, it inevitably results in dynamic energy points as a consequence of large knowledge site visitors throughout wires.” By lowering wire size, FlexGen interconnect IP can scale back total system energy and thus assist heating issues brought on by the vitality density of shifting large quantities of knowledge throughout SoC interconnects.

Determine 2 FlexNoC guide interconnect (above) is proven with one of the best efficiency, whereas automated FlexGen (under) considerably reduces the interconnect wire size. Supply: Arteris

Siwinski added that the variety of gates doesn’t matter at smaller nodes. “Energy from wire size kills you, so we scale back wire size to scale back total energy, efficiency, and space (PPA) in SoC designs.” That’s essential as SoCs scale and grow to be extra highly effective to fulfill the calls for of functions like AI, autonomous driving, and cloud computing.

FlexGen is processor agnostic and helps Arm, RISC-V, and x86 processors. Furthermore, its IP era is extremely repeatable to facilitate incremental design.

Associated Content material

• SoC Interconnect: Don’t DIY!
• What’s the future for Community-on-Chip?
• Why verification issues in network-on-chip (NoC) design
• SoC design: When is a network-on-chip (NoC) not sufficient
• Community-on-chip (NoC) interconnect topologies defined

The publish SoC interconnect automates processes, reduces wire size appeared first on EDN.

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