At a time when conventional approaches similar to Moore’s Regulation and course of scaling are struggling to maintain up with efficiency calls for, XUPs emerge as a viable candidate for synthetic intelligence (AI) and high-performance computing (HPC) functions.
However what’s an XPU? The broad consensus on its composition calls it the stitching of CPU, GPU, and reminiscence dies on a single package deal. Right here, X stands for application-specific models important for AI infrastructure.
Determine 1 An XPU integrates CPU and GPU in a single package deal to higher serve AI and HPC workloads. Supply: Broadcom
An XPU includes 4 layers: compute, reminiscence, community I/O, and dependable packaging know-how. Trade watchers name XPU the world’s largest processor. But it surely have to be designed with the appropriate ratio of accelerator, reminiscence and I/O bandwidth. And it comes with the crucial of direct or oblique reminiscence possession.
Beneath is an XPU case research that demonstrates subtle integration of compute, reminiscence, and I/O capabilities.
What’s 3.5D and F2F?
The two.5D integration, which entails integrating a number of chiplets and high-bandwidth reminiscence (HBM) modules on an interposer, has initially served AI workloads properly. Nonetheless, more and more advanced LLMs and their coaching necessitate 3D silicon stacking for extra highly effective silicon gadgets. Subsequent, 3.5D integration, which mixes 3D silicon stacking with 2.5D packaging, takes silicon gadgets to the subsequent degree with the arrival of XPUs.
That’s what Broadcom’s XDSiP claims to realize by integrating greater than 6000 mm2 of silicon and as much as 12 HBM stacks in a single package deal. And it does that by creating a face-to-face (F2F) gadget to perform vital enhancements in interconnect density and energy effectivity in comparison with the face-to-back (F2B) method.
Whereas F2B packaging is a 3D integration approach that connects the highest metallic of 1 die to the bottom of one other die, F2F connection assembles two dies ended by a high-level metallic interconnection with no thinning step. In different phrases, F2F stacking immediately connects the highest metallic layers of the highest and backside dies. That gives a dense, dependable reference to minimal electrical interference and distinctive mechanical power.
Determine 2 The F2F XPU integrates 4 compute dies with six HBM dies utilizing 3D die stacking for energy, clock, and sign interconnects. Supply: Broadcom
Broadcom’s F2F 3.5D XPU integrates 4 compute dies, one I/O die, and 6 HBM modules whereas using TSMC’s chip-on-wafer-on-substrate (CoWoS) superior packaging know-how. It claims to reduce latency between compute, reminiscence, and I/O elements inside the 3D stack whereas reaching a 7x improve in sign density between stacked dies in comparison with F2B know-how.
“Superior packaging is important for next-generation XPU clusters as we hit the bounds of Moore’s Regulation,” mentioned Frank Ostojic, senior VP and GM of the ASIC Merchandise Division at Broadcom. “By stacking chip elements vertically, Broadcom’s 3.5D platform allows chip designers to pair the appropriate fabrication processes for every element whereas shrinking the interposer and package deal measurement, resulting in vital enhancements in efficiency, effectivity, and price.”
The XPU nomenclature
Intel’s bold tackle XPUs hasn’t gone a lot far as its Falcon Shores platform is not continuing. Then again, AMD’s CPU-GPU combo has been making inroads throughout the previous couple of years. Although AMD calls it an accelerated processing unit or APU. It partly comes from the business nomenclature the place AI-specific XPUs are known as customized AI accelerators. In different phrases, it’s the customized chip that gives the processing energy to drive AI infrastructure.
Determine 3 MI300A integrates CPU and GPU cores on a single package deal to speed up the coaching of the newest AI fashions. Supply: AMD
AMD’s MI300A combines the corporate’s CDNA 3 GPU cores and x86-based Zen 4CPU cores with 128 GB of HBM3 reminiscence to ship HPC and AI workloads. El Capitan—a supercomputer housed at Lawrence Livermore Nationwide Laboratory—is powered by AMD’s MI300A APUs and is anticipated to ship greater than two exaflops of double precision efficiency when absolutely deployed.
The AI infrastructure more and more calls for specialised compute accelerators interconnected to type large clusters. Right here, whereas GPUs have develop into the de facto {hardware}, XPUs appear to signify one other viable method for heavy lifting in AI functions.
XPUs are right here, and now it’s time for software program to catch up and successfully use this brand-new processing venue for AI workloads.
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The put up AI designs and the arrival of XPUs appeared first on EDN.
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