The chiplets motion is gaining steam, and it’s obvious from how this multi-die silicon premise is dominating this system of the AI {Hardware} and Edge AI Summit to be held in San Jose, California from 10 to 12 September 2024. The annual summit focuses on deep tech and machine studying ecosystems to discover developments in synthetic intelligence (AI) infrastructure and edge deployments.
On the occasion, Alphawave Semi’s CTO Tony Chan Carusone will ship a speech on chiplets and connectivity whereas exhibiting how AI has emerged as the first catalyst for the rise of chiplet ecosystems. “The push for customized AI {hardware} is quickly evolving, and I’ll look at how chiplets ship the flexibleness required to create energy-efficient systems-in-package designs that stability value, energy, and efficiency with out ranging from scratch,” he mentioned whereas speaking about his presentation on the occasion.
Determine 1 Chiplets have performed a significant position in creating silicon options for AI, and that’s extending to 6G communication, knowledge heart networking, and high-performance computing (HPC). Supply: Alphawave Semi
On the summit, Alphawave Semi will showcase a complicated HBM3 sub-system designed for AI workloads in addition to AresCORE, a 3-nm 24-Gbps UCI built-in with TSMC CoWoS superior packaging. There will even be a reside demonstration of die-to-die (D2D) visitors at 24 Gbps per lane.
LG’s chiplet design
One other chiplets-related announcement includes main client electronics producer LG Electronics, which has created a system-in-package (SiP) encompassing chiplets with processors, DDR reminiscence interfaces, AI accelerators, and D2D interconnect. Blue Cheetah Analog Design supplied its BlueLynx D2D interconnect subsystem IP for this chiplet-based design.
Determine 2 Chiplet designs demand versatile interconnect options that reduce die-to-die latency and assist quite a lot of packaging necessities. Supply: Blue Cheetah
BlueLynx D2D interconnect gives customizable bodily (PHY) and hyperlink layer chiplet interfaces and helps each Common Chiplet Interconnect Specific (UCIe) and Bunch of Wires (BoW) requirements. Furthermore, the PHY IP options could be built-in with on-die buses utilizing fashionable requirements comparable to AMBA, CHI, AXI, and ACE.
The D2D interconnect IP is on the market for 16 nm, 12 nm, 7 nm, 6 nm, 5 nm, and 4 nm course of nodes and works on a number of fabs. It additionally facilitates each customary and superior packaging whereas supporting a number of bump pitches, metallic stacks, and orientations.
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- How the Worlds of Chiplets and Packaging Intertwine
- Chiplets advancing one design breakthrough at a time
- Chiplets diary: Three anecdotes recount design progress
- Chiplets diary: Controller IP complies with UCIe 1.1 customary
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The put up Interconnect underdogs steering chiplet design bandwagon appeared first on EDN.
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