Pulse width modulation (PWM) is a terrific foundation for digital to analog conversion. Credit score goes to options like simplicity and (theoretically) good differential and integral linearity. Sadly, PWM’s want for ripple filtering tends to make it gradual, particularly if excessive decision (upward of 8 bits) is required.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
Determine 1 presents a workaround for PWM’s lethargy through the use of it to implement solely essentially the most important 8 bits of a excessive decision (16-bit) DAC whereas a special expertise (digital potentiometer) supplies the low order 8. The 2 outputs are then passively summed in a easy 256:1 ratio resistor voltage divider. The payoff is 256 instances sooner settling (than if PWM have been used for a full 16-bit depend), mixed with 16-bit decision, monotonicity, linearity (each INL and DNL) and microvolt zero stability. The circuit lives off just some mA drawn from a single 5-V rail whereas incorporating a reasonably good voltage reference. And it’s low-cost.
Right here’s the way it works.
Determine 1 PWM most important byte (msbyte) combines with Dpot least important byte (lsbyte) to offer 16-bit decision, monotonicity, and linearity.
Incoming 3 to 5v logic, 8-bit decision PWM is inverted and level-shifted by R5C7 and high-speed AC inverter U1 to turn out to be an correct 0 to 2.50v sq. wave due to the LM4040 voltage reference and the inherent properties of CMOS logic when used as precision analog switches. The waveform is un-inverted and buffered by the opposite 5 parts of U1 to turn out to be a low impedance (~5 Ω) prime quality 0 to 100% responsibility cycle PWM output. U1’s wonderful transition symmetry (Tphl and TPlh propagation instances differ by lower than 100 ps) helps promote accuracy and linearity whereas the optimistic suggestions by means of R5 creates a latching motion that accommodates static 0% (0v) and 100% (2.5v) responsibility cycle states.
Lively low-pass analog-ripple-subtraction filtering happens by way of the R1C1 + R2C2 community as described in “Cancel PWM DAC ripple with analog subtraction”. The 4.99 kΩ x 0.1 µF = 499 µs RC time-constant proven is suitable for 16-bit (96 dB) ripple attenuation if we assume an 256/32 MHz = 8 µs PWM interval. The capacitances will in fact want proportional adjustment for various PWM clock frequencies.
In the meantime 1k Dpot U2 supplies an SPI managed, 8-bit decision, 0 to 2.5v lsbyte contribution that’s summed with the U1’s PWM output in a 256:1 ratio by the R2R3 voltage divider. The R2:R3 ratio needs to be correct and secure to raised than 0.5%. R3 is a lot larger than the two.5k (max) variable impedance offered by the pot that its contribution to nonlinearity stays lower than +/-½ lsb.
In the meantime wiper resistance results are so small as to be utterly educational.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
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- Decreasing error of digital potentiometers
- Alter op-amp acquire from -30 dB to +60 dB with one linear pot
- Op-amp wipes out DPOT wiper resistance
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The put up 8-bit PWM + 8-bit Dpot = 16-bit hybrid DAC appeared first on EDN.
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