As a style, DACs are low energy gadgets with energy and present output capabilities restricted to the milliwatt and milliampere vary. There may be, after all, no elementary motive they’ll’t be teamed up with appropriate energy output phases, which is certainly frequent sensible apply. Drawback solved.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
However only for enjoyable, this design thought takes a distinct path to energy by merging a venerable (the “L” stands for “legacy!”) LM337 regulator right into a easy (simply two generic lively chips) 8-bit PWM DAC to acquire a sturdy 1.5-A functionality. It additionally enjoys the inherent overload and thermal safety options of that time-proven Bob Pease masterpiece.
As an additional added zero price function, output voltage accuracy is (principally: ~90%) decided by the + 2% (assured, usually a lot better) precision of the LM337 inner voltage reference, somewhat than counting on the sometimes-dodgy stability of a logic provide rail as fundamental PWM DACs usually do.
Determine 1 exhibits the circuit.
Determine 1 LM337 joins forces with 4053 CMOS change to make a macho PWM DAC.
Steel gate CMOS SPDT switches U1a and U1b settle for a 10-kHz PWM 5v sign to generate a +1.25 V to -8.75 V “ADJ” management sign for the U2 regulator. ADJ = +1.25 V causes U2 to output 0 V. It has at all times struck me someway unusual {that a} adverse regulator just like the 337 typically wants a constructive management sign (on this case for Vout much less adverse than -1.25 V), nevertheless it does. ADJ = -8.75 V makes it make -10 V.
U1c generates an inverse of the PWM sign, offering lively ripple cancellation as described in “Cancel PWM DAC ripple with analog subtraction.”
Present supply Q1 reduces zero offset error by nulling the ~65 µA (typical) ADJ pin bias present. The suggestions loop established by way of R2 and R3 makes full-scale -10 V output proportional to U2’s inner reference as beforehand talked about.
This does, nonetheless, make output voltage a nonlinear operate of PWM obligation issue with performance (DF from 0 to 1): Vout = -1.25 DF / (1 – 0.875 DF) as graphed in Determine 2.
Determine 2 Graph of Vout (0 V to -10 V) versus the PWM obligation issue (0 to 1).
[Vout = -1.25 DF / (1 – 0.875 DF)]
Determine 3 plots the inverse of Determine 2, yielding the PWM DF required for a given Vout.
Determine 3 Graph of the PWM obligation issue (0 to 1) versus Vout (0 V to -10 V).
[PWM DF = Vout / (0.875*Vout – 1.25)]
For the corresponding 8-bit PWM setting Dbyte = 256 DF = 256 Vout / (0.875*Vout – 1.25).
The adverse provide rail (V-) might be something between -13 V (to accommodate U2’s minimal headroom requirement) and -15 V (in recognition of U1’s most voltage ranking). DAC accuracy might be unaffected.
U2 must be adequately heatsunk as dictated by warmth dissipation equal to output present multiplied by the V- to Vout differential. As much as double-digit Watts are doable. The 337s go into thermal shutdown at junction temperatures above 150oC, so make sure that it’s going to move the wet-forefinger-sizzle “spit take a look at!”
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
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The publish 0 V to -10 V, 1.5 A LM337 PWM energy DAC appeared first on EDN.
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