TSMC’s superior packaging capability is absolutely booked till 2025 resulting from hyper demand for giant, highly effective chips from cloud service giants like Amazon AWS, Microsoft, Google, and Meta. Nvidia and AMD are recognized to have secured TSMC’s chip-on-wafer-on-substrate (CoWoS) and system-on-integrated-chips (SoIC) capability for superior packaging.
Nvidia’s H100 chips—constructed on TSMC’s 4-nm course of—use CoWoS packaging. Then again, AMD’s MI300 sequence accelerators, manufactured on TSMC’s 5-nm and 6-nm nodes, make use of SoIC know-how for the CPU and GPU combo earlier than utilizing CoWoS for high-bandwidth reminiscence (HBM) integration.
Determine 1 CoWoS is a wafer-level system integration platform that provides a variety of interposer sizes, HBM cubes, and bundle sizes. Supply: TSMC
CoWoS is a complicated packaging know-how that provides the benefit of bigger bundle dimension and extra I/O connections. It stacks chips and packages them onto a substrate to facilitate area, energy consumption, and price advantages.
SoIC, one other superior packaging know-how created by TSMC, integrates lively and passive chips into a brand new system-on-chip (SoC) structure that’s electrically similar to native SoC. It’s a 3D heterogeneous integration know-how manufactured in front-end of line with known-good-die and gives benefits akin to excessive bandwidth density and energy effectivity.
TSMC is ramping up its superior packaging capability. It goals to triple the manufacturing of CoWoS-based wafers, producing 45,000 to 50,000 CoWoS-based items monthly by the tip of 2024. Likewise, it plans to double the capability SoIC-based wafers by the tip of this yr, manufacturing between 5,000 and 6,000 items a month. By 2025, TSMC needs to hit a month-to-month capability of 10,000 SoIC wafers.
Determine 2 SoIC is absolutely appropriate with superior packaging applied sciences like CoWoS and InFO. Supply: TSMC
Morgan Stanley analyst Charlie Chan has raised an attention-grabbing and viable query: How do corporations like TSMC decide superior packaging demand and allocate capability accordingly. What’s the benchmark that TSMC makes use of for its superior packaging clients?
Jeff Su, director of investor relations at TSMC, whereas answering Chan, acknowledged that the demand for superior packaging may be very sturdy and the capability may be very tight. He added that TSMC has greater than doubled its superior packaging capability in 2024. Furthermore, the mega-fab has leveraged its particular relationships with OSATs to satisfy buyer wants.
TSMC works carefully with OSATs, together with its Taiwan neighbor and the world’s largest IC packaging and testing firm, ASE. TSMC chief C. C. Wei additionally talked about throughout an earnings name that Amkor plans to construct a complicated packaging and testing plant subsequent to TSMC’s fab in Arizona. Then there may be information circulating in commerce media about TSMC planning to construct a complicated packaging plant in Japan.
Superior packaging is now an intrinsic a part of the AI-driven computing revolution, and the rise of chiplets will solely bolster its significance within the semiconductor ecosystem. TSMC’s frantic capability upgrades and tie-ups with OSATs level to good days for superior packaging know-how.
TSMC’s archrivals Samsung and Intel Foundry will undoubtedly be watching carefully this supply-and-demand saga for superior packaging whereas recalibrating their respective methods. We’ll proceed masking this thrilling facet of semiconductor makeover within the coming days.
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