Categories: Electronics

Supplies unveiled for scaling copper wires at 2-nm and past

A brand new materials claims to extend the performance-per-watt of chips by enabling copper wiring to scale to the 2-nm node and past whereas decreasing resistance by as a lot as 25%. This new materials with enhanced low-k dielectric materials reduces chip capacitance and strengthens logic and DRAM chips for 3D stacking.

At this yr’s SEMICON West, held from 9 to 11 July in San Francisco, California, Utilized Supplies unveiled the fabric engineering advances that stretch copper chip wiring to the 2-nm node and under. However why are these materials engineering efforts crucial now?

As Utilized Supplies’ VP of expertise, Dr. Mehul Naik, writes in his weblog, if we don’t dramatically enhance the effectivity of chips and techniques, then the expansion of synthetic intelligence (AI) computing may very well be gated by the boundaries of the facility grid. Beneath is a more in-depth have a look at this premise.

The advances in patterning and subsequently continued lithographic scaling are making it potential to print ever-smaller transistor options on a chip. Nonetheless, whereas chipmakers proceed to shrink transistors with every era, they have to additionally shrink the trenches for the wiring. And, as chipmakers additional scale the wiring, the barrier and liner take up a bigger share of the quantity supposed for wiring.

In consequence, it turns into bodily unattainable to create low-resistance, void-free copper wiring within the remaining house. That’s as a result of whereas wires get thinner, electrical resistance will increase. Furthermore, as wires get nearer collectively and the insulating dielectric materials between the wires decreases, capacitance and electrical crosstalk enhance, leading to sign delays and distortion. The end result of those wiring scaling points is slower and extra power-hungry chips.

Determine 1 To create wiring, engineers etch trenches into dielectric materials after which line them with a skinny stack of metals that sometimes features a barrier layer to stop copper from migrating into the chip, a liner to advertise copper adhesion, and eventually bulk copper that completes the sign wires. Supply: Utilized Supplies

“Whereas advances in patterning are driving continued machine scaling, crucial challenges stay in different areas, together with interconnect wiring resistance, capacitance, and reliability,” stated Solar-Jung Kim, VP and head of the Foundry Improvement Staff at Samsung Electronics. He requires supplies engineering improvements to beat these challenges.

To this point, the semiconductor trade has addressed the performance-per-watt problem by way of supplies innovation within the smallest wires closest to the transistor layer. Greater than 20 years in the past, low-dielectric-constant or “low-k” dielectrics had been launched because the insulating supplies between wires, changing aluminum wiring with copper.

The mix of low-k dielectrics and copper turned the semiconductor trade’s workhorse, repeatedly aided by unique supplies and supplies engineering methods. Nonetheless, because the trade scales to 2 nm and under, thinner dielectric materials renders chips mechanically weaker. Moreover, narrowing the copper wires creates steep will increase in electrical resistance that may cut back chip efficiency and enhance energy consumption.

That calls for brand new materials options that allow the trade to scale low-resistance copper wiring to the rising smaller nodes. “These low-k dielectric supplies should cut back capacitance and strengthen chips to take 3D stacking to new heights,” stated Dr. Prabu Raja, president of the Semiconductor Merchandise Group at Utilized Supplies. “The AI period wants extra energy-efficient computing, and chip wiring and stacking are crucial to efficiency and energy consumption.”

Utilized Supplies’ Black Diamond materials surrounds copper wires with a k-value movie engineered to cut back the buildup {of electrical} prices that enhance energy consumption and trigger interference between electrical alerts. Now, the Santa Clara, California-based firm has unveiled an enhanced model of Black Diamond, which reduces the minimal k-value to allow scaling to 2 nm and under.

Determine 2 The Producer Black Diamond PECVD dielectric movie allows chip scaling to 2 nm and under whereas providing elevated mechanical power for 3D logic and reminiscence stacking. Supply: Utilized Supplies

The improved model of Black Diamond additionally provides elevated mechanical power, which is crucial as chipmakers and techniques corporations advance 3D logic and reminiscence stacking. In keeping with Utilized Supplies, a number of logic and DRAM chipmakers have adopted the brand new Black Diamond expertise.

At SEMICON West 2024, Utilized Supplies additionally unveiled its Built-in Supplies Resolution (IMS), which mixes six totally different applied sciences in a single high-vacuum system. It features a mixture of supplies that allows chipmakers to scale copper wiring to the 2-nm node and past.

It’s a binary steel mixture of ruthenium and cobalt (RuCo), which concurrently reduces the thickness of the liner by 33% at a 2-nm node. That, in flip, produces higher floor properties for void-free copper reflow and reduces electrical line resistance by as much as 25% to enhance chip efficiency and energy consumption.

Determine 3 The brand new binary steel mixture of ruthenium and cobalt (RuCo) allows copper chip wiring to be scaled to the 2-nm node and past and reduces electrical line resistance by as a lot as 25%. Supply: Utilized Supplies

Whereas commerce media is abuzz with advances in patterning and ensuing lithographic scaling of chips, the smaller nodes can even result in copper wiring hitting bodily scaling limits. The supplies engineering advances outlined on this weblog are designed to extend the performance-per-watt of chips by enabling copper wiring to scale to the 2-nm node and past.

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The submit Supplies unveiled for scaling copper wires at 2-nm and past appeared first on EDN.

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