As an alternative of the standard method of backing up a DAC with an amplifier to spice up output, this design thought charts a much less traveled by path to energy. It integrates an LM317 constructive regulator with a easy 8-bit PWM DAC topology to acquire a sturdy 11-V, 1.5-A functionality. It thus preserves simplicity whereas exploiting the built-in fault safety options (thermal and overload) of that point confirmed Bob Pease masterpiece. Its output is proportional to the assured 2% precision of the LM317 inside voltage reference, making it securely impartial of vagaries of each the 5-V logic provide rail and incoming uncooked DC provide.
Wow the engineering world along with your distinctive design: Design Concepts Submission Information
Determine 1 diagrams the way it works.
CMOS SPDT switches U1b and U1c settle for a 10-kHz PWM sign to generate a 0 V to 9.75 V “ADJ” management sign for the U2 regulator through suggestions networks R1, 2, and R3. The incoming PWM sign is AC coupled in order that U1 can “float” on U2’s output. U1c supplies an inverse of the PWM sign, implementing lively ripple cancellation as described in “Cancel PWM DAC ripple with analog subtraction.” Notice that R1||R2 = R3 to optimize ripple subtraction and DAC accuracy.
This suggestions association does, nonetheless, make the output voltage a nonlinear operate of PWM responsibility issue (DF) as given by:
Vout = 1.25 / (1 – DF(1 – R1/(R1 + R2))
= 1.25 / (1 – 0.885*DF)
That is graphed in Determine 2.
Determine 2 The Vout (1.25 V to 11 V) versus PWM DF (0 to 1) the place Vout = 1.25 / (1 – 0.885*DF).
Determine 3 plots the inverse of Determine 2, yielding the PWM DF required for any given Vout.
Determine 3 The inverse of Determine 2 the place PWM DF = (1 – 1.25/Vout)/0.885.
The corresponding 8-bit PWM setting works out to: Dbyte = 255 (1 – 1.25 / Vout) / 0.885
Vfullscale = 1.25 / (R1/(R1 + R2)), so design selections aside from 11 V can be found. 11 V is the utmost in line with HC4053’s scores, however as much as 20 V is possible if the steel gate CD4053B is substituted for U1. Don’t overlook, nonetheless, the requirement that R3 = R1||R2.
The provision rail V+ will be something from a minimal of Vfullscale+3V to accommodate U2’s minimal headroom dropout requirement, as much as the LM317’s absmax 40-V restrict. DAC accuracy might be unaffected as a result of this chip’s glorious PSRR, though after all effectivity might endure.
U2 needs to be heatsunk as dictated by warmth dissipation attributable to required output currents multiplied by the V- to Vout differential. As much as double-digit watts is feasible at excessive currents and low Vout.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
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