Implementing enhanced wear-leveling on standalone EEPROM

Introduction/Downside

Longer helpful life and improved reliability of merchandise is changing into a extra fascinating trait. Customers count on increased high quality and extra dependable electronics, home equipment, and different gadgets on a tighter price range. Many of those functions embody embedded electronics which include on-board reminiscence like Flash or EEPROM. As system designers know, Flash and EEPROM should not have limitless erase/write endurance, besides, these reminiscences are obligatory for storing knowledge throughout operation and when the system is powered off. Subsequently, it has turn out to be frequent to make use of wear-reduction strategies which may drastically enhance embedded reminiscence longevity. One frequent methodology of wear-reduction known as wear-leveling.

Put on-leveling

When utilizing EEPROM in a design, it’s essential to think about its endurance, sometimes rated at 100,000 cycles for MCU-embedded EEPROM and 1 million cycles for standalone EEPROM at room temperature. Designers should account for this by estimating the variety of erase/write cycles over the everyday lifetime of the appliance (typically referred to as the mission profile) to find out what measurement of an EEPROM they want and easy methods to allocate knowledge inside the reminiscence.

As an illustration, in a industrial water metering system with 4 sensors for various areas of a constructing, every sensor generates a knowledge packet per utilization session, recording water quantity, session period, and timestamps. The info packets saved within the EEPROM are appended with up to date knowledge every time a brand new session happens till the packet turns into full. Knowledge is saved within the EEPROM till a central server requests a knowledge pull. The system is designed to tug knowledge often sufficient to keep away from overwriting current knowledge inside every packet. Assuming a 10-year software lifespan and a median of 400 day by day packets per sensor, the entire cycles per sensor will attain 1.46 million, surpassing the everyday EEPROM endurance ranking. To deal with this, you possibly can create a software program routine to unfold put on out throughout the extra blocks (assuming you might have extra area). That is referred to as wear-leveling.

So, how is that this applied?

To implement wear-leveling for this software, you should purchase an EEPROM twice as giant, permitting you to now allocate 2 blocks for every sensor (for a complete of two million accessible cycles per sensor). This supplies a buffer of further cycles if wanted (an additional 540 thousand cycles for every sensor on this instance).

You’ll then want some solution to know the place to jot down new knowledge to unfold the damage. Whilst you might write every block to its 1-million-cycle-limit earlier than continuing to the following, this strategy might result in untimely put on if some sensors generate extra knowledge than others. For those who unfold the damage evenly throughout the EEPROM, the general software will last more. Determine 1 illustrates the instance defined above, with 4 water meters sending knowledge packets (in purple) again to the MCU throughout the communication bus. The info is saved in blocks inside the EEPROM. Every block has a counter within the prime left indicating the variety of erase-write cycles it has skilled.

Determine 1 Business water metering, knowledge packets being saved on EEPROM, EEPROM has twice as a lot area as required. Supply: Microchip Expertise

There are two main varieties of wear-leveling: dynamic and static. Dynamic is extra fundamental and is greatest for spreading put on over a small area within the EEPROM. It can unfold put on over the reminiscence blocks whose knowledge modifications most frequently. It’s simpler to implement and requires much less overhead however may end up in uneven put on, which can be problematic as illustrated in Determine 2.

Determine 2 Dynamic wear-leveling will unfold put on over the reminiscence blocks whose knowledge modifications most frequently resulting in a failure to unfold put on evenly. Supply: Microchip Expertise

Static wear-leveling spreads put on over your entire EEPROM, extending the lifetime of your entire system. It is strongly recommended if the appliance can use your entire reminiscence as storage (e.g., if you do not want among the area to retailer important, unchanging knowledge) and can produce the very best endurance for the lifetime of the appliance. Nonetheless, it’s extra advanced to implement and requires extra CPU overhead.

Put on-leveling requires monitoring every reminiscence block’s erase/write cycles and its allocation standing, which may itself trigger put on in non-volatile reminiscence (NVM). There are a lot of intelligent methods to deal with this, however to maintain issues easy, let’s assume you retailer this data in your MCU’s RAM, which doesn’t put on out. RAM loses knowledge on energy loss, so you’ll need to design a circuit round your MCU to detect the beginnings of energy loss in order that you’ll have time to switch present register states to NVM.

The software program strategy to wear-leveling

In a software program strategy to wear-leveling, the final concept is to create an algorithm that directs the following write to the block with the least variety of writes to unfold the damage. In static wear-leveling, every write shops knowledge within the least-used location that isn’t at present allotted for anything. It additionally will swap knowledge to a brand new, unused location if the variety of cycles between the most-used and least-used block is just too giant. The variety of cycles every block has been by way of is tracked with a counter, and when the counter reaches the utmost endurance ranking, that block is assumed to have reached its anticipated lifetime and is retired.

Put on-leveling is an efficient methodology for decreasing put on and enhancing reliability. As seen in Determine 3, it permits your entire EEPROM to succeed in its most specified endurance ranking as per the datasheet. Even so, there are a couple of potentialities for enchancment. The erase/write rely of every block doesn’t signify the precise bodily well being of the reminiscence however somewhat a tough indicator of the remaining lifetime of that block. This implies the appliance is not going to detect failures that happen earlier than the rely reaches its most allowable worth. The applying additionally can not make use of 100% of the true life of every reminiscence block.

Determine 3 Put on-leveling extending the lifetime of EEPROM in software, together with blocks of reminiscence which have been retired (Purple ‘X’s). Supply: Microchip Expertise

As a result of there is no such thing as a solution to detect bodily put on out, the software program will want further checks if excessive reliability is required. One methodology is to learn again the block you simply wrote and evaluate it to the unique knowledge. This requires time on the bus, CPU overhead, and extra RAM. To detect adolescence failures, this readback should happen for each write, no less than for some period of time after the lifetime of the appliance begins. Readbacks to detect cell put on out kind failures should happen each write as soon as the variety of writes begins to strategy the endurance specification. Any time a readback doesn’t happen, the consumer won’t be able to detect any put on out and, therefore, corrupted knowledge could also be used. The next software program flowchart illustrates an instance of static wear-leveling, together with the readback and comparability obligatory to make sure high-reliability.

Determine 4 Software program flowchart illustrating static wear-leveling, together with readbacks and comparisons of reminiscence to make sure high-reliability. Supply: Microchip Expertise

The necessity to readback and evaluate the reminiscence after every write can create extreme limitations in efficiency and use of system assets. There exist some options to this out there. For instance, some EEPROMs embody error correction, which may sometimes right a single bit error out of each specified variety of bytes (e.g., 4 bytes). There are completely different error correction schemes utilized in embedded reminiscence, the most typical being Hamming codes. Error correction works by together with further bits referred to as parity bits that are calculated from the info saved within the reminiscence. When knowledge is learn again, the inner circuit recalculates the parity bits and compares them to the parity bits that had been saved. If there’s a discrepancy, this means that an error has occurred. The sample of the parity discrepancy can be utilized to pinpoint the precise location of the error. The system can then robotically right this single bit error by flipping its worth, thus restoring the integrity of the info. This helps lengthen the lifetime of a reminiscence block. Nonetheless, many EEPROMs don’t give any indication that this correction operation passed off. Subsequently, it nonetheless doesn’t clear up the issue of detecting a failure earlier than the info is misplaced.

An information-driven resolution to wear-leveling software program

To detect true bodily put on out, sure EEPROMs embody a bit flag which may be learn when a single-bit error in a block has been detected and corrected. This lets you readback and verify a single standing register to see if ECC was invoked over the past operation. This reduces the necessity for readbacks of total reminiscence blocks to double-check outcomes (Determine 5). When an error is decided to have occurred inside the block, you possibly can assume the block is degraded and may now not be used, after which retire it. Due to this, you possibly can depend on data-based suggestions to know when the reminiscence is definitely worn out as an alternative of counting on a blind counter. This basically eliminates the necessity for estimating the anticipated lifetime of reminiscence in your designs. That is nice for programs which see huge shifts of their environments over the lifetime of the top software, like dramatic temperature and voltage variations that are frequent within the manufacturing, automotive and utilities industries. Now you can lengthen the lifetime of the reminiscence cells all the way in which to true failure, doubtlessly permitting you to make use of the system even longer than the datasheet endurance specification.

Determine 5 Put on-leveling with an EEPROM with ECC and standing bit permits maximization of reminiscence lifespan by operating cells to failure, doubtlessly growing lifespan past datasheet endurance specification. Supply: Microchip Expertise

Microchip Expertise, a semiconductor producer with over 30 years of expertise producing EEPROM now provides a number of gadgets which offer a flag to inform the consumer when error-correction has occurred, in flip alerting the appliance {that a} specific block of reminiscence have to be retired.

I2C EEPROMs: 24CSM01 (1 Mbit), 24CS512 (512 Kbit), 24CS256 (256 Kbit)
SPI EEPROMs: 25CSM04 (4 Mbit), 25CS640 (64 Kbit)

This can be a data-driven strategy to wear-leveling which may additional lengthen the lifetime of the reminiscence past what commonplace wear-leveling can produce. Additionally it is extra dependable than basic wear-leveling as a result of it makes use of precise knowledge as an alternative of arbitrary counts—if one block lasts longer than one other, you possibly can proceed utilizing that block till cell put on out. This may cut back time taken on the bus, CPU overhead, and required RAM which in flip can cut back energy consumption and total system efficiency. As proven in Determine 6, the software program stream may be up to date to accommodate this new standing indicator.

Determine 6 Software program flowchart illustrating a simplified static wear-leveling routine utilizing an error correction standing indicator. Supply: Microchip Expertise

As illustrated within the flowchart, utilizing an error correction standing (ECS) bit eradicated the necessity to readback knowledge, retailer it in RAM, and carry out a whole comparability to the info simply written, release assets and making a conceptually less complicated software program stream. An information readback continues to be required (because the standing bit is just evaluated on reads), however the knowledge may be ignored and thrown out earlier than merely studying the standing bit, eliminating the necessity for extra RAM and CPU comparability overhead. The variety of occasions the software program checks the standing bit will range based mostly on the dimensions of the blocks outlined, which in flip depend upon the smallest file measurement the software program is dealing with.

The next are some benefits of the ECS bit:

Maximize EEPROM block lifespan by operating cells to failure
Choice to take away full block reads to verify for knowledge corruption, releasing up time on the communication bus
If wear-leveling is just not obligatory or too burdensome to the appliance, the ECS bit serves as a fast verify of reminiscence well being, facilitating the extension of EEPROM block lifespan and serving to to keep away from monitoring erase/write cycles

Reliability enhancements with an ECS bit

Error correction applied with a standing indicator is a robust device for enhancing reliability and increasing system life, particularly when utilized in a wear-leveling scheme. Any enhancements in reliability are extremely desired in automotive, medical, and different practical security kind functions, and are welcomed by any designer looking for to create the very best system for his or her software.

Eric Moser is a senior product advertising and marketing engineer for Microchip Expertise Inc. and is accountable for guiding the enterprise technique and advertising and marketing of a number of EEPROM and Actual Time Clock product strains. Moser has 8 years of expertise at Microchip, spending 5 years as a take a look at engineer within the 8-bit microcontroller group. Earlier than Microchip, Moser labored as an embedded programs engineer in numerous roles involving automated testbed growth, digital/mechanical prognostics, and unmanned aerial programs. Moser holds a bachelor’s diploma in programs engineering from the College of Arizona.

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