Driving excessive voltage silicon FETs in 1000-V flybacks

The 800 V automotive programs allow larger efficiency electrical autos able to driving ranges longer than 400 miles on a single cost and charging occasions as quick as 20 minutes. 800 V batteries hardly ever function at precisely 800 V and may go as excessive as 900 V with converter enter necessities as much as 1000 V.

There are a variety of energy design challenges for 1000-V-type purposes, together with field-effect transistors (FET) choice and the necessity to have a robust sufficient gate drive for >1,000 V silicon FETs which usually have bigger gate capacitances than silicon carbide (SiC) FETs. SiC FETs have the benefit of decrease whole gate cost than silicon FETs with related parameters; nevertheless, SiC usually comes with elevated value.

You’ll discover silicon FETs utilized in designs such because the Texas Devices (TI) 350 V to 1,000 V DC Enter, 56 W Flyback Remoted Energy Provide Reference Design, which cascodes two 950 V FETs in a 54 W primary-side regulated (PSR) flyback. In lower-power general-purpose bias provides (<10 W), it’s potential to make use of a single 1,200 V silicon FET in TI’s Triple Output 10W PSR Flyback Reference Design which is the main target of this energy tip.

This reference design is usually a bias provide for the remoted gate drivers of traction inverters. It features a huge enter (60 V to 1000 V) PSR flyback with three remoted 33 V outputs, 100 mA masses, and makes use of TI’s UCC28730-Q1 because the controller. Determine 1 reveals the UCC28730-Q1 datasheet with a 20-mA minimal drive present.

Determine 1 Gate-drive functionality of the UCC28730-Q1 with a 20-mA minimal drive present. Supply: Texas Devices

The problem is that the 1,200 V silicon FET could have a really massive enter capacitance (Ciss) of round 1,400 pF at 100 V VDS, which is 4 occasions greater than a equally rated SiC FET.

With a comparatively weak gate drive from the UCC28730-Q1, Equation 1 estimates the first FET turn-on time to be roughly 840 ns.

Determine 2 reveals that as FET gate-to-source capacitance (C_GS) and gate-to-drain capacitance (C_GD) will increase, it consumes the on-time of the first FET required to control the output voltage of the converter.

Determine 2 FET activate and off curves, as FET C_GS and C_GD improve, it consumes the on-time of the first FET required to control the output voltage of the converter. Supply: Texas Devices

Determine 3 reveals the undesirable impact of this by trying on the gate voltage of the UCC28730-Q1 driving the first FET immediately. On this instance, it takes roughly 800 ns to utterly activate the FET and 1.5 µs for the gate to achieve its nominal voltage. As you go to 400 V, the controller remains to be making an attempt to cost C_GD when the controller decides to show off the FET. It’s a lot worse at 1,000 V the place the C_GS remains to be being charged earlier than turning off. This reveals that because the enter voltage will increase, the controller can’t output an entire on-pulse and subsequently the converter can’t energy as much as nominal output voltage.

Determine 3 Gate voltage of UCC28730-Q1 immediately driving the first FET with growing enter voltage. Supply: Texas Devices

To unravel this, you should use a easy buffer circuit utilizing two low-cost bipolar junction transistors as proven in Determine 4.

Determine 4 Easy N-Channel P-Channel N Channel-, P-Channel N-Channel P-Channel (NPN-PNP) emitter follower gate-drive circuit. Supply: Texas Devices

Determine 5 reveals the gate present waveform of the first FET and demonstrates the buffer circuit able to gate drive currents better than 500 mA.

Determine 5 Gate drive buffer present waveform of PMP23431, demonstrating that the buffer circuit is able to gate drive present better than 500 mA. Supply: Texas Devices

As proven in Equation 2, this reduces the cost time to 33 ns and is 25 occasions quicker in comparison with simply utilizing the gate drive of the controller.

A PSR flyback structure usually requires a minimal load present to remain inside regulation. This helps improve the on-time and the converter can now energy as much as its minimal load necessities at 1000 V as proven in Determine 6. The converter’s general efficiency is within the PMP23431 take a look at report and Determine 7 reveals the switching waveform with fixed pulses on the first FET. At 1,000 V with the minimal load requirement, the on-time is roughly 1 µs. With out this buffer circuit, the converter wouldn’t energy as much as 1,000 V enter.

Determine 6 Converter startup with minimal load requirement with a 1000-V enter. Supply: Texas Devices

Determine 7 Major FET switching waveform of PMP23431 at 1000 V enter. Supply: Texas Devices

In excessive voltage purposes as much as 1,000 V, the obligation cycle might be fairly small—within the tons of of nanoseconds. A high-voltage silicon FET might be the limiting issue to attaining a well-regulated output resulting from its excessive gate capacitances. This energy tip launched PMP23431 and a easy buffer circuit to shortly cost the gate capacitances to help the decrease on-times of those excessive voltage programs.

Darwin Fernandez is a programs supervisor within the Automotive Energy Design Companies workforce at Texas Devices. He has been at TI for 14 years and has beforehand supported a number of energy product strains as an purposes engineer designing buck, flyback, and energetic clamp ahead converters. He has a BSEE and MSEE from California Polytechnic State College, San Luis Obispo.

 

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Extra Assets

1. Learn the applying be aware, “Sensible Issues in Excessive-Efficiency MOSFET, IGPT and MCT Gate-Drive Circuits.”
2. Take a look at the applying report, “Fundamentals of MOSFET and IGBT Gate Driver Circuits.”
3. Obtain the PMP41009 reference design.