Driving CMOS totem poles with logic indicators, AC coupling, and grounded gates

Regardless of large, large-scale integration being ubiquitous in up to date digital design, discrete MOSFETs within the basic CMOS totem pole topology are nonetheless typically indispensable. This makes ideas and methods for driving them effectively with logic degree indicators likewise helpful, as a result of it may be a “bit” tough, particularly if aside from commonplace logic voltage ranges are concerned. 

If (fortunately) they don’t seem to be, we’ve got Determine 1.

Determine 1 The best case of logic sign totem pole drive—direct connection works if V⁺⁺ <= V_L.

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Within the fortunate circumstance that the totem FET supply pins are linked to optimistic and adverse rails that match the logic ranges, a easy direct connection (a wire) will suffice. All that’s wanted for achievement then is that:

1. The FET ON/OFF gate-source voltage degree lies throughout the logic sign tour, and
2. The logic sign supply has ample drive to deal with the paralleled FET enter capacitances.

Merchandise 2 is especially necessary, as a result of it impacts the archenemy of totem pole effectivity, cross-conduction. 

It usually occurs that, through the transition between Q1-conducting and Q2-not to the alternative state, there might be an interval of overlap when each transistors conduct. That is “cross-conduction”, and it wastes energy, typically so much. The longer its length, the higher the waste. The length of cross-conduction is determined by the time required for the logic sign to finish the 0/1 or 1/0 transition, which is determined by how lengthy it takes to cost and discharge the respective gate enter capacitances. The cross-conduction gremlin is considerably mitigated by the actual fact the capacitance that delays one FET’s turn-off additionally delays its complementary accomplice’s turn-on, however pace remains to be very important.

Now suppose Q1’s V⁺⁺ supply voltage is greater than V_L. What now? Determine 2 reveals a easy resolution: AC coupling.

Determine 2 AC coupling can remedy the issue of optimistic rail voltage mismatch if the management sign runs constantly.

After all, this straightforward repair will solely work if the logic sign could be relied upon to at all times have an AC element. That’s to say, if solely its responsibility cycle isn’t 0% (at all times OFF) nor 100% (at all times ON): 0% < DC < 100%. C1 ought to have not less than an order of magnitude higher capacitance than Q1’s gate capacitance (e.g., 1 nF). Whereas D1 can normally be an extraordinary junction diode (e.g., 1N4148), a Schottky sort is usually a better option if a number of further tons of of mV of gate drive are wanted.

AC coupling also can come to the rescue if the totem’s adverse rail is beneath floor, as proven in Determine 3. The identical DC limitation making use of, in fact.

Determine 3 Ditto for AC coupling and adverse rail mismatch, too.

So, what to do if DC doesn’t obey the foundations, and we are able to’t depend on a easy diode to outline sign ranges? See Determine 4.

Determine 4 “Grounded” gate Q3 maintains C1 cost when logic sign stops.

Small-signal transistor Q3’s configuration as a common-gate, non-inverting high-speed amplifier transfers mandatory steady-state present to Q1. Select R2 to be a low sufficient resistance to supply Q2’s most anticipated source-to-gate leakage present (R2 = 10k will usually be a really conservative selection), then R1 = R2(V⁺⁺/V_L – 1).

And naturally, as illustrated in Determine 5, the identical trick works for a adverse totem rail.

Determine 5 Grounded gate This fall shifts logic sign to adverse rail referred C2 and Q2.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.

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