DRAM fundamentals and its quest for thermal stability by optimizing peripheral transistors

For many years, compute architectures have relied on dynamic random-access reminiscence (DRAM) as their predominant reminiscence, offering non permanent storage from which processing items retrieve knowledge and program code. The high-speed operation, giant integration density, cost-effectiveness, and wonderful reliability have contributed to the widespread adoption of DRAM expertise in lots of digital units.

DRAM bit cell—the ingredient that shops one bit of knowledge—has a really primary construction. It consists of 1 capacitor (1C) and one transistor (1T) built-in near the capacitor. Whereas the capacitor’s function is to retailer a cost, the transistor is used to entry the capacitor, both to learn how a lot cost is saved or to retailer a brand new cost.

The 1T-1C bit cells are organized in arrays containing phrase and bit strains, and the phrase line is related to the transistors’ gate, which controls entry to the capacitor. The reminiscence state could be learn by sensing the saved cost on the capacitor by way of the bit line.

Through the years, the reminiscence group launched subsequent generations of DRAM expertise, enabled by steady bit-cell density scaling. Present DRAM chips belong to the ’10-nm class’ (denoted as D1x, D1y, D1z, D1a…), the place the half pitches of the energetic space within the reminiscence cell array vary from 19 nm all the way down to 10 nm. Nonetheless, the AI-driven demand for higher performing and bigger capability DRAM is propelling R&D into past 10-nm generations.

This requires improvements in capacitors, entry transistors, and bit cell architectures. Examples of such improvements are high-aspect ratio pillar capacitors, the transfer from saddle-shaped (FinFET-based) entry transistors to vertical-gate architectures, and the transition from 6F² to 4F² cell designs—F being the minimal characteristic dimension for a given expertise node.

A more in-depth look inside a planar 1T-1C DRAM chip: The peripheral circuit

To allow full performance of the DRAM chip, a number of different transistors are wanted in addition to the entry transistors. These further transistors play a job in, for instance, the deal with decoder, sense amplifier, or output buffer operate. They’re known as DRAM peripheral transistors and are historically fabricated subsequent to the DRAM reminiscence array space.

Determine 1 The 1T-1C-based DRAM reminiscence array and DRAM peripheral space are proven inside a DRAM chip. Supply: imec

DRAM peripheral transistors could be grouped into three predominant classes. The primary class is common logic transistors: digital switches which can be repeatedly turned on and off. The second class is sense amplifiers—analog kinds of transistors that sense the distinction in cost between two-bit cells. A small optimistic change is amplified right into a excessive voltage (representing a logic 1) and a small detrimental grow to be zero voltage (representing a logical 0).

These logical values are then saved in a construction of latches known as the row buffer. The sense amplifiers sometimes reside near the reminiscence array, consuming a major space of the DRAM chip. The third class is row decoders: transistors that cross a comparatively excessive bias (sometimes round 3 V) to the reminiscence ingredient to help the write operation.

To maintain tempo with the node-to-node enchancment of the reminiscence array, the DRAM periphery evolves accordingly when it comes to space discount and efficiency enhancement. In the long run, extra disruptive options could also be envisioned that break the normal ‘2D’ DRAM chip structure. One choice is to manufacture the DRAM periphery on a separate wafer, and bond it to the wafer that comprises the reminiscence array, following an method launched in 3D NAND.

Towards a single and thermally secure platform optimized for peripheral transistors

The three teams of peripheral transistors include their very own necessities. The common logic transistors will need to have good quick channel management, excessive on present (I_on), and low off present (I_off). With these traits, they carefully resemble the logic transistors which can be a part of typical systems-on-chips (SoCs). In addition they have to allow a number of threshold voltages (V_th) to fulfill completely different design necessities.

The opposite two classes have extra dissimilar traits and don’t exist in typical logic SoCs. The analog sense amplifier requires good amplification, benefitting from a low threshold voltage (V_th). As well as, since indicators are amplified, the mismatch between two neighboring sense amplifiers have to be as little as doable. The perfect sense amplifier, due to this fact, is a really repeatable transistor with good analog performance.

Lastly, the row decoder is a digital transistor that wants an exceptionally thick gate oxide—in comparison with a sophisticated logic node—to maintain the upper bias. This makes the transistor inherently extra dependable on the expense of being slower in operation.

Determine 2 Listed below are the principle steps wanted to manufacture a transistor for DRAM peripheral purposes; the vital modules requiring particular developments are underlined. Supply: PSS

Along with these particular necessities, there are a selection of constraints that apply to all peripheral transistors. One vital problem is the thermal stability. In present DRAM course of flows with DRAM reminiscence arrays sitting subsequent to the periphery, peripheral transistors are fabricated earlier than DRAM reminiscence parts. The periphery is thus subjected to a number of thermal therapies imposed by the fabrication of the storage capacitor, entry transistor, and reminiscence back-end-of-line.

Peripheral transistors should, due to this fact, be capable to stand up to ‘DRAM reminiscence anneal’ temperatures as excessive as 550-600°C for a number of hours. Subsequent, the cost-effectiveness of DRAM chips have to be preserved, driving the mixing selections towards less complicated course of options than what logic flows are typically utilizing.

To maintain prices down, the reminiscence business additionally favors a single expertise platform for numerous peripheral transistors—regardless of their particular person wants. Moreover, there’s a extra aggressive requirement for low leakage and low energy consumption, which advantages a number of DRAM use instances, particularly cell ones.

The mix of all these specs makes a direct copy of the usual logic course of circulation inconceivable. It requires optimization of particular modules, together with the transistors’ gate stack, supply/drain junctions, and supply/drain steel contacts.

Editor’s Be aware: That is first a part of the article sequence concerning the newest developments in DRAM designs. This half focuses on DRAM fundamentals, peripheral circuits, and the journey towards a single, cost-effective, and thermally secure expertise platform optimized for peripheral transistors. The second half will present an in depth account of DRAM periphery developments.

Alessio Spessot, technical account director, has been concerned in growing superior CMOS, DRAM, NAND, rising reminiscence array, and periphery throughout his stints at Micron, Numonyx, and STMicroelectronics.

Naoto Horiguchi, director of CMOS gadget expertise at imec, has labored at Fujitsu and the College of California Santa Barbara whereas being concerned in superior CMOS gadget R&D.

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The submit DRAM fundamentals and its quest for thermal stability by optimizing peripheral transistors appeared first on EDN.

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