Check options to confront silent knowledge corruption in ICs

Whereas semiconductor design engineers turn into extra conscious of silent knowledge corruption (SDC) or silent knowledge errors (SDE) attributable to getting older, environmental elements, and different points, embedded take a look at options are rising to handle this delicate however vital problem. One such answer applies embedded deterministic take a look at patterns in-system by way of industry-standard APB or AXI bus interfaces.

Siemens EDA’s in-system take a look at controller—designed particularly to work with the corporate’s Tessent Streaming Scan Community (SSN) software program—performs deterministic testing all through the silicon lifecycle. Tessent In-System Check is constructed on the success of Siemens’ Tessent MissionMode expertise and Tessent SSN software program.

Determine 1 The Tessent In-System Check software program with embedded on-chip in-system take a look at controller (ISTC) allows the take a look at and prognosis of semiconductor chips all through the silicon lifecycle. Supply: Siemens EDA

Tessent In-System Check allows seamless integration of deterministic take a look at patterns generated with Siemens’ Tessent TestKompress software program. That enables chip designers to use embedded deterministic take a look at patterns generated utilizing Tessent TestKompress with Tessent SSN on to the in-system take a look at controller.

The ensuing deterministic take a look at patterns are utilized in-system to supply the best take a look at high quality degree inside a pre-defined take a look at window. In addition they supply the flexibility to vary take a look at content material as units mature or age by way of the silicon lifecycle.

Determine 2 Tessent In-System Check applies high-quality deterministic take a look at patterns for in-system/in-field testing through the lifecycle of a chip. Supply: Siemens EDA

These in-system exams with embedded deterministic patterns additionally assist the reuse of current take a look at infrastructure. They permit IC designers to reuse current IJTAG- and SSN-based patterns for in-system purposes whereas bettering total chip planning and decreasing take a look at time.

“Tessent In-System Check expertise permits us to reuse our intensive take a look at infrastructure and patterns already utilized in our manufacturing exams for our knowledge middle fleet,” stated Dan Trock, senior DFT supervisor at Amazon Net Providers (AWS). “This permits high-quality in-field testing of our knowledge facilities. Steady monitoring of silicon units all through their lifecycle helps to make sure AWS clients profit from infrastructure and companies of the best high quality and reliability.”

The provision of options just like the Tessent In-System Check reveals that silent knowledge corruption in ICs is now on designers’ radar and that extra options are prone to emerge to counter this problem attributable to getting older and environmental elements.

Associated Content material

• Check Compression
• Design for take a look at boot camp
• Uncovering Silent Information Errors with AI
• Check patterns are alleged to stress you out
• Understanding and combating silent knowledge corruption

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The submit Check options to confront silent knowledge corruption in ICs appeared first on EDN.

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