The open chiplet ecosystem is steadily taking form, one design demonstration at a time. Take, for example, Alphawave Semi, which has introduced the tape-out of what it claims to be the business’s first off-the-shelf multi-protocol I/O connectivity chiplet on TSMC’s 7-nm course of node.
This multi-standard I/O chiplet employs an IP portfolio grievance with Ethernet, PCIe, CXL, and Common Chiplet Interconnect Categorical (UCIe) Revision 1.1 requirements. It delivers a complete bandwidth of as much as 1.6 Tbps with as much as 16 lanes of multi-standard PHY supporting silicon-proven PCIe 6.0, CXL 3.x, and 800G Ethernet IPs.
Determine 1 The tape-out of the off-the-shelf, multi-protocol I/O connectivity chiplet demonstrates the combination of superior interfaces. Supply: Alphawave Semi
A few months in the past, Alphawave Semi introduced the event of a chiplet connectivity platform on TSMC’s 3-nm course of node. It’s a UCIe subsystem comprising PHY and controller which may ship 24 Gbps knowledge charges. The 24-Gbps UCIe subsystem is compliant with the UCIe Revision 1.1 specification and features a extremely configurable die-to-die controller that helps streaming, PCIe/CXLTM, AXI-4, AXI-S, CXS, and CHI protocols.
Determine 2 The UCIe subsystem options bit error price (BER) well being monitoring to make sure dependable operation. Supply: Alphawave Semi
Alphawave Semi demonstrated the above two designs on the Chiplet Summit 2024 in Santa Clara, California, earlier this 12 months.
In its quest to pave the best way for open chiplet ecosystems, Alphawave Semi has additionally joined palms with Arm on the compute aspect. It has just lately introduced the event of a compute chiplet constructed on Arm Neoverse Compute Subsystems (CSS) for synthetic intelligence (AI) and machine studying (ML), high-performance compute (HPC), knowledge heart, and 5G/6G networking infrastructure purposes.
Such a collaboration brings a chiplet connectivity specialist like Alphawave Semi a portfolio that features IO extension chiplets, reminiscence chiplets, and compute chiplets. Combining Arm’s compute constructing blocks with Alphawave Semi’s connectivity IP can even bolster the creation of an open chiplet ecosystem.
Determine 3 The compute chiplet combines the Arm Neoverse CSS platform with Alphawave Semi’s connectivity IPs for UCIe, 112/224G Ethernet, and HBM subsystems. Supply: Alphawave Semi
The chiplet design examples outlined above mark a transparent pattern: the developments of key chiplet constructing blocks are steadily taking form, additionally bolstering its multi-protocol ecosystem. With the maturation of chiplet requirements like UCIe and the supply of silicon-proven chiplet subsystems, design engineers can scale back growth time, decrease prices, and create larger synergy with their present {hardware} ecosystems.
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